From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5ED76C433FF for ; Tue, 13 Aug 2019 15:48:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 344C32173B for ; Tue, 13 Aug 2019 15:48:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="EteqEOXI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730219AbfHMPsS (ORCPT ); Tue, 13 Aug 2019 11:48:18 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:45240 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730209AbfHMPsQ (ORCPT ); Tue, 13 Aug 2019 11:48:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=QKrZKqm9xX7/gKntli3kjDV0bZW8VwVWFoBUswi6ZbI=; b=EteqEOXIET0tWjttOs8yG7q9iP WiRAJsSgjVccNRZwrHedX1TPYLHuuMafbM7Odac45JrZI/jyTR7s5nAu+f0OL0NF801jMg+cJxUIO RjZrmSEX48zI5QNs/XDKWf0KjxHbUvmbW/Jf6M9XtqirEDuwcrjzcj/TZHXjhTf3UvHsrE6Y9YL5P ++Ynr2cz8F3Frnmrsh/nFTR5mjv9m/DGi2IWnQzQQ5NEs5v8HNpHdw2r9JEwAmcVZukpiVGk7q0e1 lVSJN2neYYD+I1lMLiXue2JvQqneOiWljiUUAOSSf/v6Axmk+wO50Hyq5kxIW2J4f3fCGyFS4JiZD 2P52qeiA==; Received: from [2001:4bb8:180:1ec3:c70:4a89:bc61:2] (helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92 #3 (Red Hat Linux)) id 1hxZ1y-00056s-1s; Tue, 13 Aug 2019 15:48:14 +0000 From: Christoph Hellwig To: Palmer Dabbelt , Paul Walmsley Cc: Damien Le Moal , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/15] riscv: implement remote sfence.i natively for M-mode Date: Tue, 13 Aug 2019 17:47:41 +0200 Message-Id: <20190813154747.24256-10-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190813154747.24256-1-hch@lst.de> References: <20190813154747.24256-1-hch@lst.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The RISC-V ISA only supports flushing the instruction cache for the local CPU core. For normal S-mode Linux remote flushing is offloaded to machine mode using ecalls, but for M-mode Linux we'll have to do it ourselves. Use the same implementation as all the existing open source SBI implementations by just doing an IPI to all remote cores to execute th sfence.i instruction on every live core. Signed-off-by: Christoph Hellwig --- arch/riscv/mm/cacheflush.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 9ebcff8ba263..10875ea1065e 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -10,10 +10,35 @@ #include +#ifdef CONFIG_M_MODE +static void ipi_remote_fence_i(void *info) +{ + return local_flush_icache_all(); +} + +void flush_icache_all(void) +{ + on_each_cpu(ipi_remote_fence_i, NULL, 1); +} + +static void flush_icache_cpumask(const cpumask_t *mask) +{ + on_each_cpu_mask(mask, ipi_remote_fence_i, NULL, 1); +} +#else /* CONFIG_M_MODE */ void flush_icache_all(void) { sbi_remote_fence_i(NULL); } +static void flush_icache_cpumask(const cpumask_t *mask) +{ + cpumask_t hmask; + + cpumask_clear(&hmask); + riscv_cpuid_to_hartid_mask(mask, &hmask); + sbi_remote_fence_i(hmask.bits); +} +#endif /* CONFIG_M_MODE */ /* * Performs an icache flush for the given MM context. RISC-V has no direct @@ -28,7 +53,7 @@ void flush_icache_all(void) void flush_icache_mm(struct mm_struct *mm, bool local) { unsigned int cpu; - cpumask_t others, hmask, *mask; + cpumask_t others, *mask; preempt_disable(); @@ -47,9 +72,7 @@ void flush_icache_mm(struct mm_struct *mm, bool local) cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu)); local |= cpumask_empty(&others); if (mm != current->active_mm || !local) { - cpumask_clear(&hmask); - riscv_cpuid_to_hartid_mask(&others, &hmask); - sbi_remote_fence_i(hmask.bits); + flush_icache_cpumask(&others); } else { /* * It's assumed that at least one strongly ordered operation is -- 2.20.1