Re: [PATCH v3 1/3] mmc: sdhci: Add PLL Enable support to internal clock setup

["Michael K. Johnson" <johnsonm@danlj.org>]

On Thu, Aug 15, 2019 at 02:27:44PM +0300, Adrian Hunter wrote:
> On 13/08/19 1:56 AM, Michael K. Johnson wrote:
> > The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable
> > setup as part of the internal clock setup as described in 3.2.1 Internal
> > Clock Setup Sequence of SD Host Controller Simplified Specification
> > Version 4.20.  This changes the timeouts to the new specification of
> > 150ms for each step and is documented as safe for "prior versions which
> > do not support PLL Enable."
> > 
> > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> > Co-developed-by: Michael K Johnson <johnsonm@danlj.org>
> 
> Did you mean for this patch to be "From:" Ben Chuang because otherwise
> "Co-developed-by" the author is redundant.

Ben wrote the code and is the primary author. I helped with some
changes to bring it closer to normal style, so I have definitely
been a secondary co-developer. Ben's corporate email server adds a
generic confidentiality notice outside his control, and we were
informed that with that header on the email the patches could not
be accepted.  We developed it in a git repository, so that I have
not been "tainted" by the automatic confidentiality notice, and
at Ben's request I have posted the work. To credit me as primary
author would be fundamentally incorrect.

Are you saying that this work cannot be accepted until Ben chooses
an alternative email provider besides his corporate email in order
to avoid the spurious confidentiality notice, such that he is the
sender of the email?