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From: "Paul E. McKenney" <paulmck@linux.ibm.com>
To: "Björn Töpel" <bjorn.topel@gmail.com>
Cc: linux-kernel@vger.kernel.org
Subject: Re: memory-barriers.txt questions
Date: Wed, 21 Aug 2019 07:38:13 -0700	[thread overview]
Message-ID: <20190821143813.GE28441@linux.ibm.com> (raw)
In-Reply-To: <CAJ+HfNiC3jEuP39-a5PoQuY=Vi-CeQJ6STSLKZZRqSRND4Fcyw@mail.gmail.com>

On Wed, Aug 21, 2019 at 04:24:42PM +0200, Björn Töpel wrote:
> Paul,
> 
> Reaching out directly, hope that's OK!

Adding LKML on CC, hope that's OK!

> >From memory-barriers.txt (what an excellent document. I've read it
> over and over, and never get all the details. :-)):
> --8<--
> MISCELLANEOUS FUNCTIONS
> -----------------------
> 
> Other functions that imply barriers:
> 
>  (*) schedule() and similar imply full memory barriers.
> -->8--
> 
> The "and similar" part puzzles me. IPI is a a full barrier on all
> platforms (I think). Are interrupts in general full barriers? What
> more?

Functions similar to schedule() include schedule_user(),
schedule_preempt_disabled(), preempt_schedule(), preempt_schedule_irq(),
and so on.  Plus any function that calls one of these functions.

Interrupts are quite architecture specific, and on many architectures an
interrupt does not imply any sort of cross-CPU ordering in and of itself.
So you would need to inspect the interrupt-entry/-exit code to see if
the needed full memory-barrier instructions were in place to answer
this question.

But what are you trying to achieve?

							Thanx, Paul


           reply	other threads:[~2019-08-21 14:38 UTC|newest]

Thread overview: expand[flat|nested]  mbox.gz  Atom feed
 [parent not found: <CAJ+HfNiC3jEuP39-a5PoQuY=Vi-CeQJ6STSLKZZRqSRND4Fcyw@mail.gmail.com>]

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