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Thu, 22 Aug 2019 08:46:35 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K CC: Daniel Lezcano , Thomas Gleixner , Atish Patra , Alistair Francis , Damien Le Moal , Christoph Hellwig , Anup Patel , "kvm@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Anup Patel Subject: [PATCH v5 17/20] RISC-V: KVM: Implement ONE REG interface for FP registers Thread-Topic: [PATCH v5 17/20] RISC-V: KVM: Implement ONE REG interface for FP registers Thread-Index: AQHVWMYaWZQS0ZLf2EG+HLcDX2ccrw== Date: Thu, 22 Aug 2019 08:46:35 +0000 Message-ID: <20190822084131.114764-18-anup.patel@wdc.com> References: <20190822084131.114764-1-anup.patel@wdc.com> In-Reply-To: <20190822084131.114764-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR01CA0118.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:1::34) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; 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x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: reOLtwardSYXq0JRUGIJNKeCsgkDSK/2Z9kvtpwx9B5bjAKCl5qOX1A3PEMd4bszCqWCHvXO3bsFDoq0QX2vx72KtrMynS/KOFON+tIkD8Nw4jVi/5fP9QRlAYRQlcfJR+iwH3KlnxXNDZK32M8Fc025Ftm1uIUO1LT+I5VEbn+2kPPOXcU+aYnCBayyqPxq+Paq2E91hDOoGczwZtD8QA/Sh9aC4vKsspbQq28LCYsCa2NkdHxqcvgSwa6wpIw+WT8uK9cgPBwF94Iv+FmxZ7CxvHP7lm4Fq/F1JXhEigNurKNLZZgAfjhHzwJMFMyCokUjckS8gt8/9QM+8Y9vw8NcsK9VIYwJXpNY1Pvqx7uAmO7N5cqTGLZEq9x4cVgJZUcXG5EHQi2/fMxTrh4nCeamN+PoAmwI73UN+u0edg0= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: d4165ed7-e4b4-4958-4e76-08d726dd3cd9 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Aug 2019 08:46:35.4592 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Q3DQ8rsQVGJqbPTb1oM1LmFauuB8rTsSTIO+INC2JWBYSXj2gt8YmF+o1YgmjKWhGQ9mwpIlT7Y2bq46jiPFAg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6047 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Atish Patra Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating point registers such as F0-F31 and FCSR. This support is added for both 'F' and 'D' extensions. Signed-off-by: Atish Patra Signed-off-by: Anup Patel Acked-by: Paolo Bonzini Reviewed-by: Paolo Bonzini --- arch/riscv/include/uapi/asm/kvm.h | 10 +++ arch/riscv/kvm/vcpu.c | 104 ++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 024f220eb17e..c9f03363bb28 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -83,6 +83,16 @@ struct kvm_sregs { #define KVM_REG_RISCV_CSR_REG(name) \ (offsetof(struct kvm_sregs, name) / sizeof(unsigned long)) =20 +/* F extension registers are mapped as type4 */ +#define KVM_REG_RISCV_FP_F (0x04 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_FP_F_REG(name) \ + (offsetof(struct __riscv_f_ext_state, name) / sizeof(u32)) + +/* D extension registers are mapped as type 5 */ +#define KVM_REG_RISCV_FP_D (0x05 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_FP_D_REG(name) \ + (offsetof(struct __riscv_d_ext_state, name) / sizeof(u64)) + #endif =20 #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index e7c5fe09c3bc..ad7b67dc80aa 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -426,6 +426,98 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu = *vcpu, return 0; } =20 +static int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; + unsigned long isa =3D vcpu->arch.isa; + unsigned long __user *uaddr =3D + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val; + + if ((rtype =3D=3D KVM_REG_RISCV_FP_F) && + riscv_isa_extension_available(&isa, f)) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) + return -EINVAL; + if (reg_num =3D=3D KVM_REG_RISCV_FP_F_REG(fcsr)) + reg_val =3D &cntx->fp.f.fcsr; + else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <=3D reg_num) && + reg_num <=3D KVM_REG_RISCV_FP_F_REG(f[31])) + reg_val =3D &cntx->fp.f.f[reg_num]; + else + return -EINVAL; + } else if ((rtype =3D=3D KVM_REG_RISCV_FP_D) && + riscv_isa_extension_available(&isa, d)) { + if (reg_num =3D=3D KVM_REG_RISCV_FP_D_REG(fcsr)) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) + return -EINVAL; + reg_val =3D &cntx->fp.d.fcsr; + } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <=3D reg_num) && + reg_num <=3D KVM_REG_RISCV_FP_D_REG(f[31])) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u64)) + return -EINVAL; + reg_val =3D &cntx->fp.d.f[reg_num]; + } else + return -EINVAL; + } else + return -EINVAL; + + if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +static int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; + unsigned long isa =3D vcpu->arch.isa; + unsigned long __user *uaddr =3D + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val; + + if ((rtype =3D=3D KVM_REG_RISCV_FP_F) && + riscv_isa_extension_available(&isa, f)) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) + return -EINVAL; + if (reg_num =3D=3D KVM_REG_RISCV_FP_F_REG(fcsr)) + reg_val =3D &cntx->fp.f.fcsr; + else if ((KVM_REG_RISCV_FP_F_REG(f[0]) <=3D reg_num) && + reg_num <=3D KVM_REG_RISCV_FP_F_REG(f[31])) + reg_val =3D &cntx->fp.f.f[reg_num]; + else + return -EINVAL; + } else if ((rtype =3D=3D KVM_REG_RISCV_FP_D) && + riscv_isa_extension_available(&isa, d)) { + if (reg_num =3D=3D KVM_REG_RISCV_FP_D_REG(fcsr)) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u32)) + return -EINVAL; + reg_val =3D &cntx->fp.d.fcsr; + } else if ((KVM_REG_RISCV_FP_D_REG(f[0]) <=3D reg_num) && + reg_num <=3D KVM_REG_RISCV_FP_D_REG(f[31])) { + if (KVM_REG_SIZE(reg->id) !=3D sizeof(u64)) + return -EINVAL; + reg_val =3D &cntx->fp.d.f[reg_num]; + } else + return -EINVAL; + } else + return -EINVAL; + + if (copy_from_user(reg_val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -435,6 +527,12 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcp= u, return kvm_riscv_vcpu_set_reg_core(vcpu, reg); else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_CSR) return kvm_riscv_vcpu_set_reg_csr(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_F) + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_F); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_D) + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); =20 return -EINVAL; } @@ -448,6 +546,12 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcp= u, return kvm_riscv_vcpu_get_reg_core(vcpu, reg); else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_CSR) return kvm_riscv_vcpu_get_reg_csr(vcpu, reg); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_F) + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_F); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_D) + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); =20 return -EINVAL; } --=20 2.17.1