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Thu, 22 Aug 2019 08:42:45 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K CC: Daniel Lezcano , Thomas Gleixner , Atish Patra , Alistair Francis , Damien Le Moal , Christoph Hellwig , Anup Patel , "kvm@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Anup Patel Subject: [PATCH v5 02/20] RISC-V: Add bitmap reprensenting ISA features common across CPUs Thread-Topic: [PATCH v5 02/20] RISC-V: Add bitmap reprensenting ISA features common across CPUs Thread-Index: AQHVWMWR9LVkivHCeU+yKxy3T1RSlA== Date: Thu, 22 Aug 2019 08:42:45 +0000 Message-ID: <20190822084131.114764-3-anup.patel@wdc.com> References: <20190822084131.114764-1-anup.patel@wdc.com> In-Reply-To: <20190822084131.114764-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR01CA0118.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:1::34) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; 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x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: gcJf5wediclZELe6QR2ewD8XLWYYZyP/lhKemAYlyKGIwEHMLwiKUdrhCB2dle7v+zIopwnNjH3/xE4Vg4JjgJ+38GNjxHe1Lea9Jp5i4YoWhv5yV4j9hDkVSQ3gJ8N4Zm4VryAXaJoTTIXb7QjZdhGclAb2R5Ot+OFr48NpnBpXjVrYQ4Efk5c57W5UfxTpVxSTjXWKzslJZOqGdfkvSHGYSs4RhXr971Gi5+9UuONcMZnokGfesYB/bC3wMMgrhsVs93pxiMnZMHxpLPwPgza+tae4vl2JyYeqg1VpraP4RG/bO/yx/28s6gxteEn1dc1mAM1UsMYt8whYqLgbszs54akE268qaJ1XVlZIs28dNnWQ+sjegFcvB3/M/aDnm9rQLDTzCZ1bc0IDSiXfy8ugdwUgQbXWmOUuzLD8vgo= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 182bec79-4eb2-4a50-e8f3-08d726dcb3f4 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Aug 2019 08:42:45.8052 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: h/ipkH0INnQT5G/iUoxeKLPv1a84qAf3p/2Ohp6r5Yyu70gcnAVLD7nA6cuQnNM5gjJYbpuJyf0Kob4VESOw9A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB7070 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds riscv_isa bitmap which represents Host ISA features common across all Host CPUs. The riscv_isa is not same as elf_hwcap because elf_hwcap will only have ISA features relevant for user-space apps whereas riscv_isa will have ISA features relevant to both kernel and user-space apps. One of the use-case for riscv_isa bitmap is in KVM hypervisor where we will use it to do following operations: 1. Check whether hypervisor extension is available 2. Find ISA features that need to be virtualized (e.g. floating point support, vector extension, etc.) Signed-off-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 26 +++++++++++ arch/riscv/kernel/cpufeature.c | 79 ++++++++++++++++++++++++++++++++-- 2 files changed, 102 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.= h index 7ecb7c6a57b1..9b657375aa51 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -8,6 +8,7 @@ #ifndef __ASM_HWCAP_H #define __ASM_HWCAP_H =20 +#include #include =20 #ifndef __ASSEMBLY__ @@ -22,5 +23,30 @@ enum { }; =20 extern unsigned long elf_hwcap; + +#define RISCV_ISA_EXT_a ('a' - 'a') +#define RISCV_ISA_EXT_c ('c' - 'a') +#define RISCV_ISA_EXT_d ('d' - 'a') +#define RISCV_ISA_EXT_f ('f' - 'a') +#define RISCV_ISA_EXT_h ('h' - 'a') +#define RISCV_ISA_EXT_i ('i' - 'a') +#define RISCV_ISA_EXT_m ('m' - 'a') +#define RISCV_ISA_EXT_s ('s' - 'a') +#define RISCV_ISA_EXT_u ('u' - 'a') +#define RISCV_ISA_EXT_zicsr (('z' - 'a') + 1) +#define RISCV_ISA_EXT_zifencei (('z' - 'a') + 2) +#define RISCV_ISA_EXT_zam (('z' - 'a') + 3) +#define RISCV_ISA_EXT_ztso (('z' - 'a') + 4) + +#define RISCV_ISA_EXT_MAX 256 + +unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); + +#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) + +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int = bit); +#define riscv_isa_extension_available(isa_bitmap, ext) \ + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) + #endif #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.= c index b1ade9a49347..4ce71ce5e290 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -6,21 +6,64 @@ * Copyright (C) 2017 SiFive */ =20 +#include #include #include #include #include =20 unsigned long elf_hwcap __read_mostly; + +/* Host ISA bitmap */ +static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; + #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif =20 +/** + * riscv_isa_extension_base - Get base extension word + * + * @isa_bitmap ISA bitmap to use + * @returns base extension word as unsigned long value + * + * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. + */ +unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap) +{ + if (!isa_bitmap) + return riscv_isa[0]; + return isa_bitmap[0]; +} +EXPORT_SYMBOL_GPL(riscv_isa_extension_base); + +/** + * __riscv_isa_extension_available - Check whether given extension + * is available or not + * + * @isa_bitmap ISA bitmap to use + * @bit bit position of the desired extension + * @returns true or false + * + * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. + */ +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int = bit) +{ + const unsigned long *bmap =3D (isa_bitmap) ? isa_bitmap : riscv_isa; + + if (bit >=3D RISCV_ISA_EXT_MAX) + return false; + + return test_bit(bit, bmap) ? true : false; +} +EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); + void riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - size_t i; + char print_str[BITS_PER_LONG+1]; + size_t i, j, isa_len; static unsigned long isa2hwcap[256] =3D {0}; =20 isa2hwcap['i'] =3D isa2hwcap['I'] =3D COMPAT_HWCAP_ISA_I; @@ -32,8 +75,11 @@ void riscv_fill_hwcap(void) =20 elf_hwcap =3D 0; =20 + bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); + for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; + unsigned long this_isa =3D 0; =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -43,8 +89,20 @@ void riscv_fill_hwcap(void) continue; } =20 - for (i =3D 0; i < strlen(isa); ++i) + i =3D 0; + isa_len =3D strlen(isa); +#if defined(CONFIG_32BIT) + if (!strncmp(isa, "rv32", 4)) + i +=3D 4; +#elif defined(CONFIG_64BIT) + if (!strncmp(isa, "rv64", 4)) + i +=3D 4; +#endif + for (; i < isa_len; ++i) { this_hwcap |=3D isa2hwcap[(unsigned char)(isa[i])]; + if ('a' <=3D isa[i] && isa[i] <=3D 'z') + this_isa |=3D (1UL << (isa[i] - 'a')); + } =20 /* * All "okay" hart should have same isa. Set HWCAP based on @@ -55,6 +113,11 @@ void riscv_fill_hwcap(void) elf_hwcap &=3D this_hwcap; else elf_hwcap =3D this_hwcap; + + if (riscv_isa[0]) + riscv_isa[0] &=3D this_isa; + else + riscv_isa[0] =3D this_isa; } =20 /* We don't support systems with F but without D, so mask those out @@ -64,7 +127,17 @@ void riscv_fill_hwcap(void) elf_hwcap &=3D ~COMPAT_HWCAP_ISA_F; } =20 - pr_info("elf_hwcap is 0x%lx\n", elf_hwcap); + memset(print_str, 0, sizeof(print_str)); + for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + if (riscv_isa[0] & BIT_MASK(i)) + print_str[j++] =3D (char)('a' + i); + pr_info("riscv: ISA extensions %s\n", print_str); + + memset(print_str, 0, sizeof(print_str)); + for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + if (elf_hwcap & BIT_MASK(i)) + print_str[j++] =3D (char)('a' + i); + pr_info("riscv: ELF capabilities %s\n", print_str); =20 #ifdef CONFIG_FPU if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) --=20 2.17.1