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Fri, 23 Aug 2019 16:05:01 +0000 From: To: , , , , , , CC: Subject: [PATCH 0/2] mtd: spi-nor: add Global Block Unlock support Thread-Topic: [PATCH 0/2] mtd: spi-nor: add Global Block Unlock support Thread-Index: AQHVWcyE8k/5ko42FESjGCuiD3PSZw== Date: Fri, 23 Aug 2019 16:05:01 +0000 Message-ID: <20190823160452.14905-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P195CA0077.EURP195.PROD.OUTLOOK.COM (2603:10a6:802:59::30) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c4a4b1e7-ae78-40d0-9c40-08d727e3a6f7 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MN2PR11MB3789; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: c4a4b1e7-ae78-40d0-9c40-08d727e3a6f7 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Aug 2019 16:05:01.2506 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: joRRBRlJ40W9HuLyc7VthOcwfQcXTLDc2lhmRLoqu21Bcjp87Ij9YgtcXcN9IY0qT8AfchTmQLX6ebqZuwCZdHFwE34JtWuqgH2wJ/vv6fc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3789 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus This is similar with what other nor flashes are doing by clearing the block protection bits from the status register: disable the write protection after a power-on reset cycle. The Global Block-Protection Unlock command offers a single command cycle that unlocks the entire memory array. Prefer this method for higher throughput. Tested on the sst26vf064b flash using the atmel-quadspi driver. Tudor Ambarus (2): mtd: spi-nor: add Global Block Unlock support mtd: spi-nor: unlock global block protection on sst26vf064b drivers/mtd/spi-nor/spi-nor.c | 51 +++++++++++++++++++++++++++++++++++++++= ++-- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 50 insertions(+), 2 deletions(-) --=20 2.9.5