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Sat, 24 Aug 2019 12:00:45 +0000 From: To: , , , , , , CC: , Subject: [PATCH v2 5/7] mtd: spi-nor: Create a ->set_4byte() method Thread-Topic: [PATCH v2 5/7] mtd: spi-nor: Create a ->set_4byte() method Thread-Index: AQHVWnOP59CjVg8FSkOG/7b87ZQTgA== Date: Sat, 24 Aug 2019 12:00:45 +0000 Message-ID: <20190824120027.14452-6-tudor.ambarus@microchip.com> References: <20190824120027.14452-1-tudor.ambarus@microchip.com> In-Reply-To: <20190824120027.14452-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR07CA0194.eurprd07.prod.outlook.com (2603:10a6:802:3f::18) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [86.127.53.184] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f36924fb-37c9-49ed-390c-08d7288ab1e1 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MN2PR11MB3984; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: f36924fb-37c9-49ed-390c-08d7288ab1e1 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Aug 2019 12:00:45.2758 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: mLNMRB3zllFUtg4fvybEA7PjSQ2/vEzocKbUqwQYuWIeYVICFRwUMA0vIN9O8eO5BnWYTam9AdP//ntRqdjJuHXqEdLYReXpm2fH+4sgns4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3984 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Boris Brezillon The procedure used to enable 4 byte addressing mode depends on the NOR device, so let's provide a hook so that manufacturer specific handling can be implemented in a sane way. Signed-off-by: Boris Brezillon [tudor.ambarus@microchip.com: use nor->params.set_4byte() instead of nor->set_4byte()] Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 76 ++++++++++++++++++++++-----------------= ---- include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 41 insertions(+), 37 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 93424f914159..1629584be30e 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -633,6 +633,17 @@ static int macronix_set_4byte(struct spi_nor *nor, boo= l enable) NULL, 0); } =20 +static int st_micron_set_4byte(struct spi_nor *nor, bool enable) +{ + int ret; + + write_enable(nor); + ret =3D macronix_set_4byte(nor, enable); + write_disable(nor); + + return ret; +} + static int spansion_set_4byte(struct spi_nor *nor, bool enable) { nor->bouncebuf[0] =3D enable << 7; @@ -667,45 +678,24 @@ static int spi_nor_write_ear(struct spi_nor *nor, u8 = ear) return nor->write_reg(nor, SPINOR_OP_WREAR, nor->bouncebuf, 1); } =20 -/* Enable/disable 4-byte addressing mode. */ -static int set_4byte(struct spi_nor *nor, bool enable) +static int winbond_set_4byte(struct spi_nor *nor, bool enable) { - int status; - bool need_wren =3D false; - - switch (JEDEC_MFR(nor->info)) { - case SNOR_MFR_ST: - case SNOR_MFR_MICRON: - /* Some Micron need WREN command; all will accept it */ - need_wren =3D true; - /* fall through */ - case SNOR_MFR_MACRONIX: - case SNOR_MFR_WINBOND: - if (need_wren) - write_enable(nor); + int ret; =20 - status =3D macronix_set_4byte(nor, enable); - if (need_wren) - write_disable(nor); + ret =3D macronix_set_4byte(nor, enable); + if (ret || enable) + return ret; =20 - if (!status && !enable && - JEDEC_MFR(nor->info) =3D=3D SNOR_MFR_WINBOND) { - /* - * On Winbond W25Q256FV, leaving 4byte mode causes - * the Extended Address Register to be set to 1, so all - * 3-byte-address reads come from the second 16M. - * We must clear the register to enable normal behavior. - */ - write_enable(nor); - spi_nor_write_ear(nor, 0); - write_disable(nor); - } + /* + * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address + * Register to be set to 1, so all 3-byte-address reads come from the + * second 16M. We must clear the register to enable normal behavior. + */ + write_enable(nor); + ret =3D spi_nor_write_ear(nor, 0); + write_disable(nor); =20 - return status; - default: - /* Spansion style */ - return spansion_set_4byte(nor, enable); - } + return ret; } =20 static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) @@ -4153,11 +4143,18 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, static void macronix_set_default_init(struct spi_nor *nor) { nor->params.quad_enable =3D macronix_quad_enable; + nor->params.set_4byte =3D macronix_set_4byte; } =20 static void st_micron_set_default_init(struct spi_nor *nor) { nor->params.quad_enable =3D NULL; + nor->params.set_4byte =3D st_micron_set_4byte; +} + +static void winbond_set_default_init(struct spi_nor *nor) +{ + nor->params.set_4byte =3D winbond_set_4byte; } =20 /** @@ -4178,6 +4175,10 @@ static void spi_nor_manufacturer_init_params(struct = spi_nor *nor) st_micron_set_default_init(nor); break; =20 + case SNOR_MFR_WINBOND: + winbond_set_default_init(nor); + break; + default: break; } @@ -4222,6 +4223,7 @@ static void spi_nor_legacy_init_params(struct spi_nor= *nor) =20 /* Initialize legacy flash parameters and settings. */ params->quad_enable =3D spansion_quad_enable; + params->set_4byte =3D spansion_set_4byte; =20 /* Set SPI NOR sizes. */ params->size =3D (u64)info->sector_size * info->n_sectors; @@ -4610,7 +4612,7 @@ static int spi_nor_init(struct spi_nor *nor) */ WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, "enabling reset hack; may not recover from unexpected reboots\n"); - set_4byte(nor, true); + nor->params.set_4byte(nor, true); } =20 return 0; @@ -4634,7 +4636,7 @@ void spi_nor_restore(struct spi_nor *nor) /* restore the addressing mode */ if (nor->addr_width =3D=3D 4 && !(nor->flags & SNOR_F_4B_OPCODES) && nor->flags & SNOR_F_BROKEN_RESET) - set_4byte(nor, false); + nor->params.set_4byte(nor, false); } EXPORT_SYMBOL_GPL(spi_nor_restore); =20 diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index a3a765c21edc..012731ad339f 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -482,6 +482,7 @@ struct spi_nor; * @erase_map: the erase map parsed from the SFDP Sector Map Parameter * Table. * @quad_enable: enables SPI NOR quad mode. + * @set_4byte: puts the SPI NOR in 4 byte addressing mode. * @disable_block_protection: disables block protection during power-up. */ struct spi_nor_flash_parameter { @@ -495,6 +496,7 @@ struct spi_nor_flash_parameter { struct spi_nor_erase_map erase_map; =20 int (*quad_enable)(struct spi_nor *nor); + int (*set_4byte)(struct spi_nor *nor, bool enable); int (*disable_block_protection)(struct spi_nor *nor); }; =20 --=20 2.9.5