From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD11EC3A5A4 for ; Mon, 26 Aug 2019 10:47:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A118D20828 for ; Mon, 26 Aug 2019 10:47:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=yadro.com header.i=@yadro.com header.b="ALFSZARy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729614AbfHZKrH (ORCPT ); Mon, 26 Aug 2019 06:47:07 -0400 Received: from mta-02.yadro.com ([89.207.88.252]:52204 "EHLO mta-01.yadro.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726616AbfHZKrH (ORCPT ); Mon, 26 Aug 2019 06:47:07 -0400 Received: from localhost (unknown [127.0.0.1]) by mta-01.yadro.com (Postfix) with ESMTP id 8419741207; Mon, 26 Aug 2019 10:47:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=yadro.com; h= content-type:content-type:content-transfer-encoding:mime-version :x-mailer:message-id:date:date:subject:subject:from:from :received:received:received; s=mta-01; t=1566816424; x= 1568630825; bh=E0To92lhfBhY9mEETsPSthtYRPyNoja4M5DFFsTt9Ls=; b=A LFSZARyfhqWZ0wv/zS+CIhcPTOLiRshZGcTrNxWggrezE6NMBDO2Zzx4biq3zkhF xzpoTdWFpQtDrj07Szv56ALheb7oiVfkNSpup4XmoSR6k3gNW3n3hHIBbhtoYPNP dcKVeYh1zEsGhbbh3gMH4B0+saEniXUZwgIGqaNBGc= X-Virus-Scanned: amavisd-new at yadro.com Received: from mta-01.yadro.com ([127.0.0.1]) by localhost (mta-01.yadro.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yfcsvvo-M9Rz; Mon, 26 Aug 2019 13:47:04 +0300 (MSK) Received: from T-EXCH-02.corp.yadro.com (t-exch-02.corp.yadro.com [172.17.10.102]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mta-01.yadro.com (Postfix) with ESMTPS id 3768B41206; Mon, 26 Aug 2019 13:47:02 +0300 (MSK) Received: from localhost.dev.yadro.com (172.17.15.69) by T-EXCH-02.corp.yadro.com (172.17.10.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.669.32; Mon, 26 Aug 2019 13:47:02 +0300 From: Ivan Mikhaylov To: Guenter Roeck , Wim Van Sebroeck CC: Joel Stanley , Andrew Jeffery , , , , , Alexander Amelkin , , Rob Herring , Mark Rutland , , Ivan Mikhaylov Subject: [PATCH v2 0/4] add dual-boot support Date: Mon, 26 Aug 2019 13:46:32 +0300 Message-ID: <20190826104636.19324-1-i.mikhaylov@yadro.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.17.15.69] X-ClientProxiedBy: T-EXCH-01.corp.yadro.com (172.17.10.101) To T-EXCH-02.corp.yadro.com (172.17.10.102) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ASPEED SoCs support dual-boot feature for SPI Flash. When strapped appropriately, the SoC starts wdt2 (/dev/watchdog1) and if within a minute it is not disabled, it goes off and reboots the SoC from an alternate SPI Flash chip by changing CS0 controls to actually drive CS1 line. When booted from alternate chip, in order to access the main chip at CS0, the user must reset the appropriate bit in the watchdog hardware. There is no interface that would allow to do that from an embedded firmware startup script. This commit implements support for that feature: * Enable 'alt-boot' option for wdt2 * Enable secondary SPI flash chip * Make it possible to get access to the primary SPI flash chip at CS0 after booting from the alternate chip at CS1. A sysfs interface is added to provide an easy way for embedded firmware startup scripts to clear the chip select bit to gain access to the primary flash chip in order to allow for recovery of its contents. Ivan Mikhaylov (4): vesnin: add wdt2 section with alt-boot option vesnin: add secondary SPI flash chip watchdog/aspeed: add support for dual boot dt-bindings/watchdog: Add access_cs0 option for alt-boot .../bindings/watchdog/aspeed-wdt.txt | 7 +++ arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 12 ++++ drivers/watchdog/aspeed_wdt.c | 62 ++++++++++++++++++- 3 files changed, 80 insertions(+), 1 deletion(-) -- 2.20.1