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Mon, 26 Aug 2019 12:09:02 +0000 From: To: , , , , , , CC: , Subject: [RESEND PATCH v3 10/20] mtd: spi-nor: Rework the SPI NOR lock/unlock logic Thread-Topic: [RESEND PATCH v3 10/20] mtd: spi-nor: Rework the SPI NOR lock/unlock logic Thread-Index: AQHVXAcFrCpvcaMjzkSkkB6kiMDMIg== Date: Mon, 26 Aug 2019 12:08:50 +0000 Message-ID: <20190826120821.16351-11-tudor.ambarus@microchip.com> References: <20190826120821.16351-1-tudor.ambarus@microchip.com> In-Reply-To: <20190826120821.16351-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR09CA0046.eurprd09.prod.outlook.com (2603:10a6:802:28::14) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 47bfae3d-6cee-4005-73f4-08d72a1e27b0 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MN2PR11MB3678; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 47bfae3d-6cee-4005-73f4-08d72a1e27b0 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Aug 2019 12:08:50.1704 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: qNQ7+67AFc/xFcM/eaLYrHxc9hIXFTLHpnKA3Hvnu5oEK2caxnFpSJ+t/aH26TsvhFdH+cjSAYbI0WOQ2Wxkf6XaieuBEU6MlqLpUNw/q8M= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3678 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Boris Brezillon Add the SNOR_F_HAS_LOCK flag and set it when SPI_NOR_HAS_LOCK is set in the flash_info entry or when it's a Micron or ST flash. Move the locking hooks in a separate struct so that we have just one field to update when we change the locking implementation. Signed-off-by: Boris Brezillon [tudor.ambarus@microchip.com: use ->default_init() hook, introduce spi_nor_late_init_params(), set ops in nor->params] Signed-off-by: Tudor Ambarus --- v3: no changes, clear_sr_bp() is handled in the last patch of the series. drivers/mtd/spi-nor/spi-nor.c | 50 ++++++++++++++++++++++++++++++++-------= ---- include/linux/mtd/spi-nor.h | 23 ++++++++++++++------ 2 files changed, 53 insertions(+), 20 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 235e82a121a1..3f997797fa9d 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1598,6 +1598,12 @@ static int stm_is_locked(struct spi_nor *nor, loff_t= ofs, uint64_t len) return stm_is_locked_sr(nor, ofs, len, status); } =20 +static const struct spi_nor_locking_ops stm_locking_ops =3D { + .lock =3D stm_lock, + .unlock =3D stm_unlock, + .is_locked =3D stm_is_locked, +}; + static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) { struct spi_nor *nor =3D mtd_to_spi_nor(mtd); @@ -1607,7 +1613,7 @@ static int spi_nor_lock(struct mtd_info *mtd, loff_t = ofs, uint64_t len) if (ret) return ret; =20 - ret =3D nor->flash_lock(nor, ofs, len); + ret =3D nor->params.locking_ops->lock(nor, ofs, len); =20 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK); return ret; @@ -1622,7 +1628,7 @@ static int spi_nor_unlock(struct mtd_info *mtd, loff_= t ofs, uint64_t len) if (ret) return ret; =20 - ret =3D nor->flash_unlock(nor, ofs, len); + ret =3D nor->params.locking_ops->unlock(nor, ofs, len); =20 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); return ret; @@ -1637,7 +1643,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, lo= ff_t ofs, uint64_t len) if (ret) return ret; =20 - ret =3D nor->flash_is_locked(nor, ofs, len); + ret =3D nor->params.locking_ops->is_locked(nor, ofs, len); =20 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); return ret; @@ -4148,6 +4154,7 @@ static void macronix_set_default_init(struct spi_nor = *nor) =20 static void st_micron_set_default_init(struct spi_nor *nor) { + nor->flags =3D SNOR_F_HAS_LOCK; nor->params.quad_enable =3D NULL; nor->params.set_4byte =3D st_micron_set_4byte; } @@ -4292,6 +4299,23 @@ static void spi_nor_info_init_params(struct spi_nor = *nor) } =20 /** + * spi_nor_late_init_params() - Late initialization of default flash param= eters. + * @nor: pointer to a 'struct spi_nor' + * + * Used to set default flash parameters and settings when the ->default_in= it() + * hook or the SFDP parser let voids. + */ +static void spi_nor_late_init_params(struct spi_nor *nor) +{ + /* + * NOR protection support. When locking_ops are not provided, we pick + * the default ones. + */ + if (nor->flags & SNOR_F_HAS_LOCK && !nor->params.locking_ops) + nor->params.locking_ops =3D &stm_locking_ops; +} + +/** * spi_nor_init_params() - Initialize the flash's parameters and settings. * @nor: pointer to a 'struct spi-nor'. * @@ -4316,6 +4340,10 @@ static void spi_nor_info_init_params(struct spi_nor = *nor) * Please not that there is a ->post_bfpt() fixup hook that can overwri= te the * flash parameters and settings imediately after parsing the Basic Fla= sh * Parameter Table. + * + * 4/ Late default flash parameters initialization, used when the + * ->default_init() hook or the SFDP parser do not set specific params. + * spi_nor_late_init_params() */ static void spi_nor_init_params(struct spi_nor *nor) { @@ -4326,6 +4354,8 @@ static void spi_nor_init_params(struct spi_nor *nor) if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) && !(nor->info->flags & SPI_NOR_SKIP_SFDP)) spi_nor_sfdp_init_params(nor); + + spi_nor_late_init_params(nor); } =20 static int spi_nor_select_read(struct spi_nor *nor, @@ -4707,6 +4737,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *nam= e, if (info->flags & SPI_S3AN) nor->flags |=3D SNOR_F_READY_XSR_RDY; =20 + if (info->flags & SPI_NOR_HAS_LOCK) + nor->flags |=3D SNOR_F_HAS_LOCK; + /* * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up * with the software protection bits set. @@ -4731,16 +4764,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *na= me, mtd->_read =3D spi_nor_read; mtd->_resume =3D spi_nor_resume; =20 - /* NOR protection support for STmicro/Micron chips and similar */ - if (JEDEC_MFR(info) =3D=3D SNOR_MFR_ST || - JEDEC_MFR(info) =3D=3D SNOR_MFR_MICRON || - info->flags & SPI_NOR_HAS_LOCK) { - nor->flash_lock =3D stm_lock; - nor->flash_unlock =3D stm_unlock; - nor->flash_is_locked =3D stm_is_locked; - } - - if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) { + if (nor->params.locking_ops) { mtd->_lock =3D spi_nor_lock; mtd->_unlock =3D spi_nor_unlock; mtd->_is_locked =3D spi_nor_is_locked; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 7da89dd483cb..ea3bcac54dc2 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -243,6 +243,7 @@ enum spi_nor_option_flags { SNOR_F_BROKEN_RESET =3D BIT(6), SNOR_F_4B_OPCODES =3D BIT(7), SNOR_F_HAS_4BAIT =3D BIT(8), + SNOR_F_HAS_LOCK =3D BIT(9), }; =20 /** @@ -466,6 +467,18 @@ enum spi_nor_pp_command_index { struct spi_nor; =20 /** + * struct spi_nor_locking_ops - SPI NOR locking methods + * @lock: lock a region of the SPI NOR. + * @unlock: unlock a region of the SPI NOR. + * @is_locked: check if a region of the SPI NOR is completely locked + */ +struct spi_nor_locking_ops { + int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); + int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); + int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); +}; + +/** * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings. * Includes legacy flash parameters and settings that can be overwritten * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216 @@ -483,6 +496,7 @@ struct spi_nor; * Table. * @quad_enable: enables SPI NOR quad mode. * @set_4byte: puts the SPI NOR in 4 byte addressing mode. + * @locking_ops: SPI NOR locking methods. */ struct spi_nor_flash_parameter { u64 size; @@ -496,6 +510,8 @@ struct spi_nor_flash_parameter { =20 int (*quad_enable)(struct spi_nor *nor); int (*set_4byte)(struct spi_nor *nor, bool enable); + + const struct spi_nor_locking_ops *locking_ops; }; =20 /** @@ -536,10 +552,6 @@ struct flash_info; * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR * at the offset @offs; if not provided by the driver, * spi-nor will send the erase opcode via write_reg() - * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR - * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR - * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is - * completely locked * @clear_sr_bp: [FLASH-SPECIFIC] clears the Block Protection Bits from * the SPI NOR Status Register. * @params: [FLASH-SPECIFIC] SPI-NOR flash parameters and settings. @@ -579,9 +591,6 @@ struct spi_nor { size_t len, const u_char *write_buf); int (*erase)(struct spi_nor *nor, loff_t offs); =20 - int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); - int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); - int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); int (*clear_sr_bp)(struct spi_nor *nor); struct spi_nor_flash_parameter params; =20 --=20 2.9.5