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Mon, 26 Aug 2019 12:09:07 +0000 From: To: , , , , , , CC: , Subject: [RESEND PATCH v3 16/20] mtd: spi-nor: Add the SPI_NOR_XSR_RDY flag Thread-Topic: [RESEND PATCH v3 16/20] mtd: spi-nor: Add the SPI_NOR_XSR_RDY flag Thread-Index: AQHVXAcM/ZWa5nusDk2eFvW+kEyFdA== Date: Mon, 26 Aug 2019 12:09:02 +0000 Message-ID: <20190826120821.16351-17-tudor.ambarus@microchip.com> References: <20190826120821.16351-1-tudor.ambarus@microchip.com> In-Reply-To: <20190826120821.16351-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR09CA0046.eurprd09.prod.outlook.com (2603:10a6:802:28::14) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 4e67c631-0694-43c1-3416-08d72a1e2ec7 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MN2PR11MB3678; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 4e67c631-0694-43c1-3416-08d72a1e2ec7 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Aug 2019 12:09:02.0575 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Fs+tNooJm9CXAhV/Svd7tpXac5A7b2n63IZjl6SrifiiHyR0XB8UuLjV4kdGDFMxMg4XBNlCjWYhEiojhlIO13WQXJHQGPiJj/k1hx6Jze4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3678 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Boris Brezillon S3AN flashes use a specific opcode to read the status register. We currently use the SPI_S3AN flag to decide whether this specific SR read opcode should be used, but SPI_S3AN is about to disappear, so let's add a new flag. Note that we use the same bit as SPI_S3AN implies SPI_NOR_XSR_RDY and vice versa. Signed-off-by: Boris Brezillon Signed-off-by: Tudor Ambarus --- v3: no changes drivers/mtd/spi-nor/spi-nor.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index edf1c8badac9..2699e999d21a 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -211,6 +211,14 @@ struct flash_info { * bit. Must be used with * SPI_NOR_HAS_LOCK. */ +#define SPI_NOR_XSR_RDY BIT(10) /* + * S3AN flashes have specific opcode to + * read the status register. + * Flags SPI_NOR_XSR_RDY and SPI_S3AN + * use the same bit as one implies the + * other, but we will get rid of + * SPI_S3AN soon. + */ #define SPI_S3AN BIT(10) /* * Xilinx Spartan 3AN In-System Flash * (MFR cannot be used for probing @@ -4798,7 +4806,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *nam= e, * spi_nor_wait_till_ready(). Xilinx S3AN share MFR * with Atmel spi-nor */ - if (info->flags & SPI_S3AN) + if (info->flags & SPI_NOR_XSR_RDY) nor->flags |=3D SNOR_F_READY_XSR_RDY; =20 if (info->flags & SPI_NOR_HAS_LOCK) --=20 2.9.5