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Mon, 26 Aug 2019 12:08:42 +0000 From: To: , , , , , , CC: , Subject: [RESEND PATCH v3 06/20] mtd: spi-nor: Add a default_init() fixup hook for gd25q256 Thread-Topic: [RESEND PATCH v3 06/20] mtd: spi-nor: Add a default_init() fixup hook for gd25q256 Thread-Index: AQHVXAcAicnY5H8dpUCDa+wa3xawzQ== Date: Mon, 26 Aug 2019 12:08:42 +0000 Message-ID: <20190826120821.16351-7-tudor.ambarus@microchip.com> References: <20190826120821.16351-1-tudor.ambarus@microchip.com> In-Reply-To: <20190826120821.16351-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR09CA0046.eurprd09.prod.outlook.com (2603:10a6:802:28::14) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 118c30ca-ab4b-4b46-daee-08d72a1e22fb x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MN2PR11MB3776; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 118c30ca-ab4b-4b46-daee-08d72a1e22fb X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Aug 2019 12:08:42.3219 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3vAQ6Hx1XnTm+IZ+mYyeQCFEKR0qnCdMSq200B6ph7Y8c6dMVzxAebFVHH/8u9PYdczNJ6TEuM645nn+jchYqJA7TYFvMuf3UU0ZBCCmBTU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3776 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Boris Brezillon gd25q256 needs to tweak the ->quad_enable() implementation and the ->default_init() fixup hook is the perfect place to do that. This way, if we ever need to tweak more things for this flash, we won't have to add new fields in flash_info. We can get rid of the flash_info->quad_enable field as gd25q256 was the only user. Signed-off-by: Boris Brezillon [tudor.ambarus@microchip.com: use ->default_init() hook instead of ->post_sfdp()] Signed-off-by: Tudor Ambarus --- v3: no changes drivers/mtd/spi-nor/spi-nor.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 8fd60e1eebd2..3dbbfe34d1d2 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -222,8 +222,6 @@ struct flash_info { =20 /* Part specific fixup hooks. */ const struct spi_nor_fixups *fixups; - - int (*quad_enable)(struct spi_nor *nor); }; =20 #define JEDEC_MFR(info) ((info)->id[0]) @@ -2126,6 +2124,21 @@ static struct spi_nor_fixups mx25l25635_fixups =3D { .post_bfpt =3D mx25l25635_post_bfpt_fixups, }; =20 +static void gd25q256_default_init(struct spi_nor *nor) +{ + /* + * Some manufacturer like GigaDevice may use different + * bit to set QE on different memories, so the MFR can't + * indicate the quad_enable method for this case, we need + * to set it in the default_init fixup hook. + */ + nor->params.quad_enable =3D macronix_quad_enable; +} + +static struct spi_nor_fixups gd25q256_fixups =3D { + .default_init =3D gd25q256_default_init, +}; + /* NOTE: double check command sets and memory organization when you add * more nor chips. This current list focusses on newer chips, which * have been converging on command sets which including JEDEC ID. @@ -2218,7 +2231,7 @@ static const struct flash_info spi_nor_ids[] =3D { "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - .quad_enable =3D macronix_quad_enable, + .fixups =3D &gd25q256_fixups, }, =20 /* Intel/Numonyx -- xxxs33b */ @@ -4237,15 +4250,6 @@ static int spi_nor_init_params(struct spi_nor *nor) params->quad_enable =3D spansion_quad_enable; break; } - - /* - * Some manufacturer like GigaDevice may use different - * bit to set QE on different memories, so the MFR can't - * indicate the quad_enable method for this case, we need - * set it in flash info list. - */ - if (info->quad_enable) - params->quad_enable =3D info->quad_enable; } =20 spi_nor_manufacturer_init_params(nor); --=20 2.9.5