From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF284C3A5A3 for ; Tue, 27 Aug 2019 13:25:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8D5432054F for ; Tue, 27 Aug 2019 13:25:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730150AbfH0NZK (ORCPT ); Tue, 27 Aug 2019 09:25:10 -0400 Received: from foss.arm.com ([217.140.110.172]:44808 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730076AbfH0NZI (ORCPT ); Tue, 27 Aug 2019 09:25:08 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6B8FE28; Tue, 27 Aug 2019 06:25:07 -0700 (PDT) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BA87A3F246; Tue, 27 Aug 2019 06:25:06 -0700 (PDT) Date: Tue, 27 Aug 2019 14:25:05 +0100 From: Andrew Murray To: Xiaowei Bao Cc: "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , Leo Li , "kishon@ti.com" , "lorenzo.pieralisi@arm.co" , "arnd@arndb.de" , "gregkh@linuxfoundation.org" , "M.h. Lian" , Mingkai Hu , Roy Zang , "jingoohan1@gmail.com" , "gustavo.pimentel@synopsys.com" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linuxppc-dev@lists.ozlabs.org" Subject: Re: [PATCH v2 07/10] PCI: layerscape: Modify the MSIX to the doorbell way Message-ID: <20190827132504.GL14582@e119886-lin.cambridge.arm.com> References: <20190822112242.16309-1-xiaowei.bao@nxp.com> <20190822112242.16309-7-xiaowei.bao@nxp.com> <20190823135816.GH14582@e119886-lin.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Aug 24, 2019 at 12:08:40AM +0000, Xiaowei Bao wrote: > > > > -----Original Message----- > > From: Andrew Murray > > Sent: 2019年8月23日 21:58 > > To: Xiaowei Bao > > Cc: bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com; > > shawnguo@kernel.org; Leo Li ; kishon@ti.com; > > lorenzo.pieralisi@arm.co; arnd@arndb.de; gregkh@linuxfoundation.org; M.h. > > Lian ; Mingkai Hu ; Roy > > Zang ; jingoohan1@gmail.com; > > gustavo.pimentel@synopsys.com; linux-pci@vger.kernel.org; > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > > linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org > > Subject: Re: [PATCH v2 07/10] PCI: layerscape: Modify the MSIX to the > > doorbell way > > > > On Thu, Aug 22, 2019 at 07:22:39PM +0800, Xiaowei Bao wrote: > > > The layerscape platform use the doorbell way to trigger MSIX interrupt > > > in EP mode. > > > > > > > I have no problems with this patch, however... > > > > Are you able to add to this message a reason for why you are making this > > change? Did dw_pcie_ep_raise_msix_irq not work when func_no != 0? Or did > > it work yet dw_pcie_ep_raise_msix_irq_doorbell is more efficient? > > The fact is that, this driver is verified in ls1046a platform of NXP before, and ls1046a don't > support MSIX feature, so I set the msix_capable of pci_epc_features struct is false, > but in other platform, e.g. ls1088a, it support the MSIX feature, I verified the MSIX > feature in ls1088a, it is not OK, so I changed to another way. Thanks. Right, so the existing pci-layerscape-ep.c driver never supported MSIX yet it erroneously had a switch case statement to call dw_pcie_ep_raise_msix_irq which would never get used. Now that we're adding a platform with MSIX support the existing dw_pcie_ep_raise_msix_irq doesn't work (for this platform) so we are adding a different method. Given that dw_pcie_ep_raise_msix_irq is used by pcie-designware-plat.c we can assume this function at least works for it's use case. Please update the commit message - It would be helpful to suggest that dw_pcie_ep_raise_msix_irq was never called in the exisitng driver because msix_capable was always set to false. Thanks, Andrew Murray > > > > > Thanks, > > > > Andrew Murray > > > > > Signed-off-by: Xiaowei Bao > > > --- > > > v2: > > > - No change. > > > > > > drivers/pci/controller/dwc/pci-layerscape-ep.c | 3 ++- > > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c > > > b/drivers/pci/controller/dwc/pci-layerscape-ep.c > > > index 8461f62..7ca5fe8 100644 > > > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c > > > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c > > > @@ -74,7 +74,8 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, > > u8 func_no, > > > case PCI_EPC_IRQ_MSI: > > > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); > > > case PCI_EPC_IRQ_MSIX: > > > - return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); > > > + return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no, > > > + interrupt_num); > > > default: > > > dev_err(pci->dev, "UNKNOWN IRQ type\n"); > > > return -EINVAL; > > > -- > > > 2.9.5 > > >