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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: cR1oyeeZG/jPT/xJWmwmVQSv1t8cTBDVI7WWT5Ns0amA2Kc6pCiR4lvaeoUf1DMJ1dsKVfmxpDu5YNuCUfeUrp90A0qb4zW+OvBxpLuRcau+b+J5jwyq1MZVXp55vrU+paMEwxbD33qkR1OAndTfKQVnWP+GpTOxwLIQIWZQOot/UvBsmHBqiCKcEfrPMMqZknJrqL3cE4LHU9M0tjCS0XuKM5FNT80usVKVH7L461maMM2VEE9FmMsM5Kms5uCsASairUYqnSfZ1nps4I3nBVXSNYC+qpgWSbh+tQabkJ8vDhT7QejXjTY1MvTwtRuOz5T7vJdo5eSMbEjXJuSdFy26idOdeturZefODlwgphvLLUAf7Cy5vE1PXzyK2vK1DLWYklXFuZvdzRiQpgxdxMHDKYceqGahYTmWVcQrvSA= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e1325b0-5fbc-4e1b-b998-08d731f862df X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Sep 2019 11:58:38.0612 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: uZNikT4EHGYDLXuq6+DWsTd3SWktVFSGuq67cm0kneks+mdMk/4cH4khMTxkIUEit1A+3s58ME3GKAnL3Cz0Hf0OyXsELCYtv3yO6jq+XXU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB3805 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Stoica Cosmin-Stefan Add initial version of device tree for S32V234-EVB, including nodes for the 4 Cortex-A53 cores, AIPS bus with UART modules, ARM architected timer and Generic Interrupt Controller (GIC). Keep SoC level separate from board level to let future boards with this SoC share common properties, while the dts files will keep board-dependent properties. Signed-off-by: Stoica Cosmin-Stefan Signed-off-by: Mihaela Martinas Signed-off-by: Dan Nica Signed-off-by: Larisa Grigore Signed-off-by: Phu Luu An Signed-off-by: Stefan-Gabriel Mirea --- arch/arm64/boot/dts/freescale/Makefile | 2 + arch/arm64/boot/dts/freescale/s32v234-evb.dts | 25 ++++ arch/arm64/boot/dts/freescale/s32v234.dtsi | 139 ++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32v234-evb.dts create mode 100644 arch/arm64/boot/dts/freescale/s32v234.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index c043aca66572..9aff21324146 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -26,3 +26,5 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-librem5-devkit.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-zii-ultra-rmb3.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-zii-ultra-zest.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-mek.dtb + +dtb-$(CONFIG_ARCH_S32) +=3D s32v234-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/s32v234-evb.dts b/arch/arm64/boo= t/dts/freescale/s32v234-evb.dts new file mode 100644 index 000000000000..4b802518cefc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32v234-evb.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + */ + +/dts-v1/; +#include "s32v234.dtsi" + +/ { + model =3D "NXP S32V234-EVB2 Board"; + compatible =3D "fsl,s32v234-evb", "fsl,s32v234"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/d= ts/freescale/s32v234.dtsi new file mode 100644 index 000000000000..37225191ccbf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + */ + +#include + +/memreserve/ 0x80000000 0x00010000; + +/ { + compatible =3D "fsl,s32v234"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x0>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x80000000>; + next-level-cache =3D <&cluster0_l2_cache>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x1>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x80000000>; + next-level-cache =3D <&cluster0_l2_cache>; + }; + + cpu2: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x100>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x80000000>; + next-level-cache =3D <&cluster1_l2_cache>; + }; + + cpu3: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x101>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x80000000>; + next-level-cache =3D <&cluster1_l2_cache>; + }; + + cluster0_l2_cache: l2-cache0 { + compatible =3D "cache"; + }; + + cluster1_l2_cache: l2-cache1 { + compatible =3D "cache"; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + /* clock-frequency might be modified by u-boot, depending on the + * chip version. + */ + clock-frequency =3D <10000000>; + }; + + gic: interrupt-controller@7d001000 { + compatible =3D "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + reg =3D <0 0x7d001000 0 0x1000>, + <0 0x7d002000 0 0x2000>, + <0 0x7d004000 0 0x2000>, + <0 0x7d006000 0 0x2000>; + interrupts =3D ; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + ranges; + + aips0: aips-bus@40000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + reg =3D <0x0 0x40000000 0x0 0x7D000>; + ranges; + + uart0: serial@40053000 { + compatible =3D "fsl,s32v234-linflexuart"; + reg =3D <0x0 0x40053000 0x0 0x1000>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + aips1: aips-bus@40080000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + reg =3D <0x0 0x40080000 0x0 0x70000>; + ranges; + + uart1: serial@400bc000 { + compatible =3D "fsl,s32v234-linflexuart"; + reg =3D <0x0 0x400bc000 0x0 0x1000>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + }; +}; --=20 2.22.0