From: "Michael K. Johnson" <johnsonm@danlj.org>
To: ulf.hansson@linaro.org
Cc: adrian.hunter@intel.com, linux-mmc@vger.kernel.org,
linux-kernel@vger.kernel.org,
"ben.chuang@genesyslogic.com.tw Ben Chuang"
<benchuanggli@gmail.com>
Subject: Re: [PATCH V9 5/5] mmc: host: sdhci-pci: Add Genesys Logic GL975x support
Date: Wed, 18 Sep 2019 06:47:34 -0400 [thread overview]
Message-ID: <20190918104734.GA3320@people.danlj.org> (raw)
In-Reply-To: <2d08c47490a349d7ee5682749f68604adc62f19f.1568184581.git.benchuanggli@gmail.com>
I see that the first four patches made it into Linus's kernel
yesterday. Is there any chance of this final patch that actually
enables the hardware making it into another pull request still
intended for 5.4? Waiting on additional acked-by on Ben's work
addressing all the review comments?
Thanks.
On Wed, Sep 11, 2019 at 03:23:44PM +0800, Ben Chuang wrote:
> From: Ben Chuang <ben.chuang@genesyslogic.com.tw>
>
> Add support for the GL9750 and GL9755 chipsets.
>
> Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/
> GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor
> tuning flow for GL9750.
next prev parent reply other threads:[~2019-09-18 10:47 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-11 7:21 [PATCH V9 0/5] " Ben Chuang
2019-09-11 7:22 ` [PATCH V9 1/5] mmc: sdhci: Change timeout of loop for checking internal clock stable Ben Chuang
2019-09-11 7:23 ` [PATCH V9 2/5] mmc: sdhci: Add PLL Enable support to internal clock setup Ben Chuang
2019-09-11 7:23 ` [PATCH V9 3/5] PCI: Add Genesys Logic, Inc. Vendor ID Ben Chuang
2019-09-11 7:23 ` [PATCH V9 4/5] mmc: sdhci: Export sdhci_abort_tuning function symbol Ben Chuang
2019-09-11 7:23 ` [PATCH V9 5/5] mmc: host: sdhci-pci: Add Genesys Logic GL975x support Ben Chuang
2019-09-18 10:47 ` Michael K. Johnson [this message]
2019-09-18 11:07 ` Adrian Hunter
2019-09-19 1:50 ` Ben Chuang
2019-09-23 21:39 ` Michael K. Johnson
2019-09-27 18:49 ` Ulf Hansson
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