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Wed, 18 Sep 2019 16:34:57 +0000 From: "Natarajan, Janakarajan" To: "linux-pm@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Thomas Renninger , Shuah Khan , Pu Wen , Borislav Petkov , Allison Randal , Thomas Gleixner , Kate Stewart , Greg Kroah-Hartman , Richard Fontana , "Natarajan, Janakarajan" Subject: [PATCH 1/2] Modify cpupower to schedule itself on cores it is reading MSRs from Thread-Topic: [PATCH 1/2] Modify cpupower to schedule itself on cores it is reading MSRs from Thread-Index: AQHVbj8CzXj8hQvM60aQ8slBTBcq3w== Date: Wed, 18 Sep 2019 16:34:57 +0000 Message-ID: <20190918163445.129103-1-Janakarajan.Natarajan@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0501CA0039.namprd05.prod.outlook.com (2603:10b6:803:41::16) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f325311e-4a9b-4ab2-a1ae-08d73c56248b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600167)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2605; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: f325311e-4a9b-4ab2-a1ae-08d73c56248b X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Sep 2019 16:34:57.6717 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: AWFoT12rY+X7kJCAeNkPLdfkc2OcywuMV5MbuOIeMHkJipo6+R5EbJIRbF1/I4OqpQYDzGzT0t+aUMbSlEPMog== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2605 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Modify cpupower to schedule itself on each of the cpus in the system and then get the APERF/MPERF register values. This is advantageous because an IPI is not generated when a read_msr() is executed on the local logical CPU thereby reducing the chance of having APERF and MPERF being out of sync. Signed-off-by: Janakarajan Natarajan --- .../utils/idle_monitor/mperf_monitor.c | 38 ++++++++++++++----- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c b/tool= s/power/cpupower/utils/idle_monitor/mperf_monitor.c index 44806a6dae11..8b072e39c897 100644 --- a/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c +++ b/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 #include =20 @@ -86,15 +87,33 @@ static int mperf_get_tsc(unsigned long long *tsc) return ret; } =20 +static int get_aperf_mperf(int cpu, unsigned long long *aval, + unsigned long long *mval) +{ + cpu_set_t set; + int ret; + + CPU_ZERO(&set); + CPU_SET(cpu, &set); + if (sched_setaffinity(getpid(), sizeof(set), &set) =3D=3D -1) { + dprint("Could not migrate to cpu: %d\n", cpu); + return 1; + } + + ret =3D read_msr(cpu, MSR_APERF, aval); + ret |=3D read_msr(cpu, MSR_MPERF, mval); + + return ret; +} + static int mperf_init_stats(unsigned int cpu) { - unsigned long long val; + unsigned long long aval, mval; int ret; =20 - ret =3D read_msr(cpu, MSR_APERF, &val); - aperf_previous_count[cpu] =3D val; - ret |=3D read_msr(cpu, MSR_MPERF, &val); - mperf_previous_count[cpu] =3D val; + ret =3D get_aperf_mperf(cpu, &aval, &mval); + aperf_previous_count[cpu] =3D aval; + mperf_previous_count[cpu] =3D mval; is_valid[cpu] =3D !ret; =20 return 0; @@ -102,13 +121,12 @@ static int mperf_init_stats(unsigned int cpu) =20 static int mperf_measure_stats(unsigned int cpu) { - unsigned long long val; + unsigned long long aval, mval; int ret; =20 - ret =3D read_msr(cpu, MSR_APERF, &val); - aperf_current_count[cpu] =3D val; - ret |=3D read_msr(cpu, MSR_MPERF, &val); - mperf_current_count[cpu] =3D val; + ret =3D get_aperf_mperf(cpu, &aval, &mval); + aperf_current_count[cpu] =3D aval; + mperf_current_count[cpu] =3D mval; is_valid[cpu] =3D !ret; =20 return 0; --=20 2.17.1