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Wed, 18 Sep 2019 16:35:00 +0000 From: "Natarajan, Janakarajan" To: "linux-pm@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Thomas Renninger , Shuah Khan , Pu Wen , Borislav Petkov , Allison Randal , Thomas Gleixner , Kate Stewart , Greg Kroah-Hartman , Richard Fontana , "Natarajan, Janakarajan" Subject: [PATCH 2/2] Update cpupower to use the RDPRU instruction Thread-Topic: [PATCH 2/2] Update cpupower to use the RDPRU instruction Thread-Index: AQHVbj8CkLjjoC195k6Z0xrn14yRmA== Date: Wed, 18 Sep 2019 16:34:59 +0000 Message-ID: <20190918163445.129103-2-Janakarajan.Natarajan@amd.com> References: <20190918163445.129103-1-Janakarajan.Natarajan@amd.com> In-Reply-To: <20190918163445.129103-1-Janakarajan.Natarajan@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0501CA0039.namprd05.prod.outlook.com (2603:10b6:803:41::16) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; 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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 0Ifvlyea1XI9BXqRtFTh9PGTYp6KPL7N73f8rsJdAy9I93J8RWxTyM6Od7XGEj+OKQs6vsTNq5BN9OO0Ga8OabzsgVNWvQD7p2d/YvYsBoBsUCp642veWjD/2cAyBNcGDYNUP7Cb/w/j54l9BGQ2SnmAJ0VPetWMNP5qtIbO07+28+vdiB5azJ0IpEkhMbBv9GkZQeagDXEiPKcVEHDEJYE0/i7pX7nUT3FCaYY1wsIFt6wMLFp4TwhFn9fGQ/DBOH2IW4TaYzVW2V5pIF20/KPaZgWNNkZn/nk8x60of04GNRibxnZikWe5JCPT3SsPeEyc9f9sQukeOziSdoVmFRfsiZsxBXNuCwGGEPx/8iDMyxcM/CUx8zjSX9aTXkA7fIMCppGnnqRDi/CDYe/7oW5Gea3zhlTRRlLOGYL5s+I= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: cc16f252-59c6-48d5-e313-08d73c56253f X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Sep 2019 16:34:59.1439 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WKR4N3l6D+wEuSwJ2d3uS39375Zn4gz2cW6fFdACYhxWag6twcDDwuZxqJgzFRT422qnu3W0CDacaaZnEDXvIQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2815 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AMD Zen 2 introduces the RDPRU instruction which can be used to access some processor registers which are typically only accessible in privilege level 0. ECX specifies the register to read and EDX:EAX will contain the value re= ad. ECX: 0 - Register MPERF 1 - Register APERF This has the added advantage of not having to use the msr module, since the userspace to kernel transitions which occur during each read_msr() might cause APERF and MPERF to go out of sync. Signed-off-by: Janakarajan Natarajan --- tools/power/cpupower/utils/helpers/cpuid.c | 4 ++++ tools/power/cpupower/utils/helpers/helpers.h | 1 + .../utils/idle_monitor/mperf_monitor.c | 20 +++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/tools/power/cpupower/utils/helpers/cpuid.c b/tools/power/cpupo= wer/utils/helpers/cpuid.c index 5cc39d4e23ed..73bfafc60e9b 100644 --- a/tools/power/cpupower/utils/helpers/cpuid.c +++ b/tools/power/cpupower/utils/helpers/cpuid.c @@ -131,6 +131,10 @@ int get_cpu_info(struct cpupower_cpu_info *cpu_info) if (ext_cpuid_level >=3D 0x80000007 && (cpuid_edx(0x80000007) & (1 << 9))) cpu_info->caps |=3D CPUPOWER_CAP_AMD_CBP; + + if (ext_cpuid_level >=3D 0x80000008 && + cpuid_ebx(0x80000008) & (1 << 4)) + cpu_info->caps |=3D CPUPOWER_CAP_AMD_RDPRU; } =20 if (cpu_info->vendor =3D=3D X86_VENDOR_INTEL) { diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpu= power/utils/helpers/helpers.h index 357b19bb136e..c258eeccd05f 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h @@ -69,6 +69,7 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN =3D 0, X86_V= ENDOR_INTEL, #define CPUPOWER_CAP_HAS_TURBO_RATIO 0x00000010 #define CPUPOWER_CAP_IS_SNB 0x00000020 #define CPUPOWER_CAP_INTEL_IDA 0x00000040 +#define CPUPOWER_CAP_AMD_RDPRU 0x00000080 =20 #define CPUPOWER_AMD_CPBDIS 0x02000000 =20 diff --git a/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c b/tool= s/power/cpupower/utils/idle_monitor/mperf_monitor.c index 8b072e39c897..faee00c078b0 100644 --- a/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c +++ b/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c @@ -20,6 +20,10 @@ #define MSR_APERF 0xE8 #define MSR_MPERF 0xE7 =20 +#define RDPRU ".byte 0x0f, 0x01, 0xfd" +#define RDPRU_ECX_MPERF 0 +#define RDPRU_ECX_APERF 1 + #define MSR_TSC 0x10 =20 #define MSR_AMD_HWCR 0xc0010015 @@ -90,6 +94,8 @@ static int mperf_get_tsc(unsigned long long *tsc) static int get_aperf_mperf(int cpu, unsigned long long *aval, unsigned long long *mval) { + unsigned long low_a, high_a; + unsigned long low_m, high_m; cpu_set_t set; int ret; =20 @@ -100,6 +106,20 @@ static int get_aperf_mperf(int cpu, unsigned long long= *aval, return 1; } =20 + if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_RDPRU) { + asm volatile(RDPRU + : "=3Da" (low_a), "=3Dd" (high_a) + : "c" (RDPRU_ECX_APERF)); + asm volatile(RDPRU + : "=3Da" (low_m), "=3Dd" (high_m) + : "c" (RDPRU_ECX_MPERF)); + + *aval =3D ((low_a) | (high_a) << 32); + *mval =3D ((low_m) | (high_m) << 32); + + return 0; + } + ret =3D read_msr(cpu, MSR_APERF, aval); ret |=3D read_msr(cpu, MSR_MPERF, mval); =20 --=20 2.17.1