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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id a10sm9997797wrv.64.2019.09.19.02.38.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Sep 2019 02:38:13 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com Cc: Neil Armstrong , linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] clk: meson: clk-pll: always enable a critical PLL when setting the rate Date: Thu, 19 Sep 2019 11:38:09 +0200 Message-Id: <20190919093809.21364-1-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190919093627.21245-1-narmstrong@baylibre.com> References: <20190919093627.21245-1-narmstrong@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make sure we always enable a PLL on a set_rate() when the PLL is flagged as critical. This fixes the case when the Amlogic G12A SYS_PLL gets disabled by the PSCI firmware when resuming from suspend-to-memory, in the case where the CPU was not clocked by the SYS_PLL, but by the fixed PLL fixed divisors. In this particular case, when changing the PLL rate, CCF doesn't handle the fact the PLL could have been disabled in the meantime and set_rate() only changes the rate and never enables it again. Fixes: d6e81845b7d9 ("clk: meson: clk-pll: check if the clock is already enabled') Signed-off-by: Neil Armstrong --- drivers/clk/meson/clk-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index ddb1e5634739..8c5adccb7959 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -379,7 +379,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, } /* If the pll is stopped, bail out now */ - if (!enabled) + if (!(hw->init->flags & CLK_IS_CRITICAL) && !enabled) return 0; if (meson_clk_pll_enable(hw)) { -- 2.22.0