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Tue, 24 Sep 2019 07:46:29 +0000 From: To: , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v2 11/22] mtd: spi-nor: Rework spi_nor_read/write_sr2() Thread-Topic: [PATCH v2 11/22] mtd: spi-nor: Rework spi_nor_read/write_sr2() Thread-Index: AQHVcqws4BSMXyqrs0alxYsMfkKjqA== Date: Tue, 24 Sep 2019 07:46:28 +0000 Message-ID: <20190924074533.6618-12-tudor.ambarus@microchip.com> References: <20190924074533.6618-1-tudor.ambarus@microchip.com> In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR0101CA0082.eurprd01.prod.exchangelabs.com (2603:10a6:800:1f::50) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e3155a01-5dbc-4778-2200-08d740c34ed6 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600167)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MN2PR11MB4319; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: e3155a01-5dbc-4778-2200-08d740c34ed6 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Sep 2019 07:46:28.7048 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: P9GnJMsxFXWq8/IdftvEkJqN9khyNY3I0ZVPwEg2J/u02R8TCKk+adZBr4zGp9SN3ROGpi0MHh7pQbln2mmitXEHxQvn04UDWiWB9H1D7fQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4319 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Move the methods up in the file, where the other Register operations reside. The error is reported inside each SR2 function, to spare the callers of duplicating code. Constify sr2 in spi_nor_write_sr2(). Do the spi_nor_write_enable() and spi_nor_wait_till_ready() inside spi_nor_write_sr2(), as the spi_nor_write_sr() does. While modyfing sr2_bit7_quad_enable(), add a new line for better code readability. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 118 ++++++++++++++++++++++++++------------= ---- 1 file changed, 74 insertions(+), 44 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 31a4622d1eb9..33130ee84164 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -731,6 +731,74 @@ static int spi_nor_write_sr(struct spi_nor *nor, const= u8 *sr, size_t len) return ret; } =20 +/** + * spi_nor_write_sr2() - Write the Status Register 2 using the + * SPINOR_OP_WRSR2 (3eh) command. + * @nor: pointer to 'struct spi_nor'. + * @sr2: buffer to write to the Status Register. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) +{ + int ret; + + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, sr2, 1)); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, + sr2, 1); + } + + if (ret) + dev_err(nor->dev, "error while writing Status Register 2\n"); + + ret =3D spi_nor_wait_till_ready(nor); + + return ret; +} + +/** + * spi_nor_read_sr2() - Read the Status Register 2 using the + * SPINOR_OP_RDSR2 (3fh) command. + * @nor: pointer to 'struct spi_nor' + * @sr2: buffer where the value of the Status Register will be written. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(1, sr2, 1)); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, + sr2, 1); + } + + if (ret) + dev_err(nor->dev, "error while reading Status Register 2\n"); + + return ret; +} + static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) { return mtd->priv; @@ -1890,36 +1958,6 @@ static int spansion_read_cr_quad_enable(struct spi_n= or *nor) return 0; } =20 -static int spi_nor_write_sr2(struct spi_nor *nor, u8 *sr2) -{ - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, sr2, 1)); - - return spi_mem_exec_op(nor->spimem, &op); - } - - return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1); -} - -static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) -{ - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, sr2, 1)); - - return spi_mem_exec_op(nor->spimem, &op); - } - - return nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1); -} - /** * sr2_bit7_quad_enable() - set QE bit in Status Register 2. * @nor: pointer to a 'struct spi_nor' @@ -1941,31 +1979,23 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor= ) ret =3D spi_nor_read_sr2(nor, sr2); if (ret) return ret; + if (*sr2 & SR2_QUAD_EN_BIT7) return 0; =20 /* Update the Quad Enable bit. */ *sr2 |=3D SR2_QUAD_EN_BIT7; =20 - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - ret =3D spi_nor_write_sr2(nor, sr2); - if (ret < 0) { - dev_err(nor->dev, "error while writing status register 2\n"); - return -EINVAL; - } - - ret =3D spi_nor_wait_till_ready(nor); - if (ret < 0) { - dev_err(nor->dev, "timeout while writing status register 2\n"); + if (ret) return ret; - } =20 /* Read back and check it. */ ret =3D spi_nor_read_sr2(nor, sr2); - if (!(ret > 0 && (*sr2 & SR2_QUAD_EN_BIT7))) { + if (ret) + return ret; + + if (!(*sr2 & SR2_QUAD_EN_BIT7)) { dev_err(nor->dev, "SR2 Quad bit not set\n"); return -EINVAL; } --=20 2.9.5