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Tue, 24 Sep 2019 07:46:18 +0000 From: To: , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v2 08/22] mtd: spi-nor: Rework write_enable/disable() Thread-Topic: [PATCH v2 08/22] mtd: spi-nor: Rework write_enable/disable() Thread-Index: AQHVcqwmGxayarzEFkyHj/sWgnNJNg== Date: Tue, 24 Sep 2019 07:46:18 +0000 Message-ID: <20190924074533.6618-9-tudor.ambarus@microchip.com> References: <20190924074533.6618-1-tudor.ambarus@microchip.com> In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR0101CA0082.eurprd01.prod.exchangelabs.com (2603:10a6:800:1f::50) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: fe1bc4f1-191c-446b-829b-08d740c348fd x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600167)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:MN2PR11MB4319; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: fe1bc4f1-191c-446b-829b-08d740c348fd X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Sep 2019 07:46:18.6176 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: APKNyq7MaovMYI0/TLIEdYplpoYKXV0h6cATBXJFgZeyf/SEbTpayYEKnpyjH+hr2XT+UvRPNJQDU5oc0S5ybzP8dc3WqKn0c19RI+6je9I= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4319 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus static int write_enable(struct spi_nor *nor) static int write_disable(struct spi_nor *nor) become static int spi_nor_write_enable(struct spi_nor *nor) static int spi_nor_write_disable(struct spi_nor *nor) Check for errors after each call to them. Move them up in the file as the first SPI NOR Register Operations, to avoid further forward declarations. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 175 +++++++++++++++++++++++++++++---------= ---- 1 file changed, 120 insertions(+), 55 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 0fb124bd2e77..0aee068a5835 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -389,6 +389,64 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,= loff_t to, size_t len, } =20 /** + * spi_nor_write_enable() - Set write enable latch with Write Enable comma= nd. + * @nor: pointer to 'struct spi_nor' + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_enable(struct spi_nor *nor) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, + NULL, 0); + } + + if (ret) + dev_err(nor->dev, "error %d on Write Enable\n", ret); + + return ret; +} + +/** + * spi_nor_write_disable() - Send Write Disable instruction to the chip. + * @nor: pointer to 'struct spi_nor' + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_disable(struct spi_nor *nor) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, + NULL, 0); + } + + if (ret) + dev_err(nor->dev, "error %d on Write Disable\n", ret); + + return ret; +} + +/** * spi_nor_read_sr() - Read the Status Register. * @nor: pointer to 'struct spi_nor' * @sr: buffer where the value of the Status Register will be written. @@ -500,43 +558,6 @@ static int write_sr(struct spi_nor *nor, u8 val) nor->bouncebuf, 1); } =20 -/* - * Set write enable latch with Write Enable command. - * Returns negative if error occurred. - */ -static int write_enable(struct spi_nor *nor) -{ - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); - - return spi_mem_exec_op(nor->spimem, &op); - } - - return nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, NULL, 0); -} - -/* - * Send write disable instruction to the chip. - */ -static int write_disable(struct spi_nor *nor) -{ - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_DATA); - - return spi_mem_exec_op(nor->spimem, &op); - } - - return nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); -} - static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) { return mtd->priv; @@ -645,9 +666,15 @@ static int st_micron_set_4byte(struct spi_nor *nor, bo= ol enable) { int ret; =20 - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + ret =3D macronix_set_4byte(nor, enable); - write_disable(nor); + if (ret) + return ret; + + ret =3D spi_nor_write_disable(nor); =20 return ret; } @@ -701,9 +728,15 @@ static int winbond_set_4byte(struct spi_nor *nor, bool= enable) * Register to be set to 1, so all 3-byte-address reads come from the * second 16M. We must clear the register to enable normal behavior. */ - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + ret =3D spi_nor_write_ear(nor, 0); - write_disable(nor); + if (ret) + return ret; + + ret =3D spi_nor_write_disable(nor); =20 return ret; } @@ -1219,7 +1252,9 @@ static int spi_nor_erase_multi_sectors(struct spi_nor= *nor, u64 addr, u32 len) list_for_each_entry_safe(cmd, next, &erase_list, list) { nor->erase_opcode =3D cmd->opcode; while (cmd->count) { - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto destroy_erase_cmd_list; =20 ret =3D spi_nor_erase_sector(nor, addr); if (ret) @@ -1274,7 +1309,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) if (len =3D=3D mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { unsigned long timeout; =20 - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto erase_err; =20 if (erase_chip(nor)) { ret =3D -EIO; @@ -1302,7 +1339,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) /* "sector"-at-a-time erase */ } else if (spi_nor_has_uniform_erase(nor)) { while (len) { - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto erase_err; =20 ret =3D spi_nor_erase_sector(nor, addr); if (ret) @@ -1323,7 +1362,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct= erase_info *instr) goto erase_err; } =20 - write_disable(nor); + ret =3D spi_nor_write_disable(nor); =20 erase_err: spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); @@ -1336,7 +1375,10 @@ static int write_sr_and_check(struct spi_nor *nor, u= 8 status_new, u8 mask) { int ret; =20 - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + ret =3D write_sr(nor, status_new); if (ret) return ret; @@ -1681,7 +1723,9 @@ static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr= ) { int ret; =20 - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 if (nor->spimem) { struct spi_mem_op op =3D @@ -1733,7 +1777,9 @@ static int macronix_quad_enable(struct spi_nor *nor) if (nor->bouncebuf[0] & SR_QUAD_EN_MX) return 0; =20 - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX); =20 @@ -1936,7 +1982,9 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) /* Update the Quad Enable bit. */ *sr2 |=3D SR2_QUAD_EN_BIT7; =20 - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 ret =3D spi_nor_write_sr2(nor, sr2); if (ret < 0) { @@ -1978,7 +2026,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) if (ret) return ret; =20 - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; =20 ret =3D write_sr(nor, nor->bouncebuf[0] & ~mask); if (ret) { @@ -2601,7 +2651,9 @@ static int sst_write(struct mtd_info *mtd, loff_t to,= size_t len, if (ret) return ret; =20 - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto unlock_and_unprep; =20 nor->sst_write_second =3D false; =20 @@ -2640,14 +2692,19 @@ static int sst_write(struct mtd_info *mtd, loff_t t= o, size_t len, } nor->sst_write_second =3D false; =20 - write_disable(nor); + ret =3D spi_nor_write_disable(nor); + if (ret) + goto sst_write_err; + ret =3D spi_nor_wait_till_ready(nor); if (ret) goto sst_write_err; =20 /* Write out trailing byte if it exists. */ if (actual !=3D len) { - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto sst_write_err; =20 nor->program_opcode =3D SPINOR_OP_BP; ret =3D spi_nor_write_data(nor, to, 1, buf + actual); @@ -2658,11 +2715,16 @@ static int sst_write(struct mtd_info *mtd, loff_t t= o, size_t len, ret =3D spi_nor_wait_till_ready(nor); if (ret) goto sst_write_err; - write_disable(nor); + + ret =3D spi_nor_write_disable(nor); + if (ret) + goto sst_write_err; + actual +=3D 1; } sst_write_err: *retlen +=3D actual; +unlock_and_unprep: spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); return ret; } @@ -2710,7 +2772,10 @@ static int spi_nor_write(struct mtd_info *mtd, loff_= t to, size_t len, =20 addr =3D spi_nor_convert_addr(nor, addr); =20 - write_enable(nor); + ret =3D spi_nor_write_enable(nor); + if (ret) + goto write_err; + ret =3D spi_nor_write_data(nor, addr, page_remain, buf + i); if (ret < 0) goto write_err; --=20 2.9.5