From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1885AECE587 for ; Tue, 1 Oct 2019 16:44:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D7EA22168B for ; Tue, 1 Oct 2019 16:44:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569948296; bh=heI1w7nY6McwTvjkvsOTZmwnaKryPkblh2fn31KdwDI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=jM2fF287fuPXnwMPv7bRw7duEV7slypsf11om2vfiFfKwQ5sjAadNJ6T5kQXJHGSE EXXVNMNp5YRJnrmxAw0Lfa2pckAOMU22rtpbFh3XZDaEUS7f0pNfeIimZuYA56nQw/ D9iplm7r+CH+5TjmlEyEwcuOnshg2GqAL5hMCSPA= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390114AbfJAQoy (ORCPT ); Tue, 1 Oct 2019 12:44:54 -0400 Received: from mail.kernel.org ([198.145.29.99]:56988 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390027AbfJAQok (ORCPT ); Tue, 1 Oct 2019 12:44:40 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7C1A721D80; Tue, 1 Oct 2019 16:44:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569948280; bh=heI1w7nY6McwTvjkvsOTZmwnaKryPkblh2fn31KdwDI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p3JxL0QehT9RtB9drhPvLC52XGzR9N3YIxQCrJYTh/gbv7r1Gd2bRCuw1GMh9twRL msK9whXgfgtQKZIzzMWwK5fdlfW4VpWKupjZJ54ru5XUZb6CZI+iGrdPv57FVkPB99 c13OgzZEKf3jAdKlWZsehMbgzqom34WgojIlJW1E= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Fabrice Gasnier , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Thierry Reding , Sasha Levin , linux-pwm@vger.kernel.org Subject: [PATCH AUTOSEL 4.14 13/29] pwm: stm32-lp: Add check in case requested period cannot be achieved Date: Tue, 1 Oct 2019 12:44:07 -0400 Message-Id: <20191001164423.16406-13-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191001164423.16406-1-sashal@kernel.org> References: <20191001164423.16406-1-sashal@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabrice Gasnier [ Upstream commit c91e3234c6035baf5a79763cb4fcd5d23ce75c2b ] LPTimer can use a 32KHz clock for counting. It depends on clock tree configuration. In such a case, PWM output frequency range is limited. Although unlikely, nothing prevents user from requesting a PWM frequency above counting clock (32KHz for instance): - This causes (prd - 1) = 0xffff to be written in ARR register later in the apply() routine. This results in badly configured PWM period (and also duty_cycle). Add a check to report an error is such a case. Signed-off-by: Fabrice Gasnier Reviewed-by: Uwe Kleine-König Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/pwm/pwm-stm32-lp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c index 9793b296108ff..3f2e4ef695d75 100644 --- a/drivers/pwm/pwm-stm32-lp.c +++ b/drivers/pwm/pwm-stm32-lp.c @@ -59,6 +59,12 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, /* Calculate the period and prescaler value */ div = (unsigned long long)clk_get_rate(priv->clk) * state->period; do_div(div, NSEC_PER_SEC); + if (!div) { + /* Clock is too slow to achieve requested period. */ + dev_dbg(priv->chip.dev, "Can't reach %u ns\n", state->period); + return -EINVAL; + } + prd = div; while (div > STM32_LPTIM_MAX_ARR) { presc++; -- 2.20.1