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received-spf: None (protection.outlook.com: wavecomp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: c6ks9cX5dYcPxi7uPV1n4z1Wm5ToFFHkt2GHB7u935/bVkaYx9XI7oecMEACZCaKUO04Hcg+MXKnoJQ2UA4TP/NPQ3eyZamjRD7bMY+OvVTenrSSgRMcMPrJgg6lSGelRI61VdJ8GM7yKGhduFHccV7NsODXxiq+R4Ic8mhZkgN4zw88BZ/WiW29T305Vtmrmlg/sObDsKFrGJBwfl79mOQSudIjDt6YWzM+07BVYRmkBdZEeYg8j6o/wz3T19PgEi66yem3pR0b/7GjIrr4Rz55CB1Hur+9XB44yS7s0Bhk4zvoNSEpt70Eklv3tZMt3u667YuRBUeBhR4ajhSShH+G2BwLqmDPzP7pwzWoTwGVsh8/7YpO8niSBpQfpUUYF92DcTaf+2vxZDbSkfM1XyU3Id/E2pKxjdBvTpG5RyQ= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: 468e0ca3-ee65-49c3-4969-08d746b9cb81 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Oct 2019 21:53:29.4475 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: OX7LwPCZnvbTKg2EQrBMW4QMfNLCw3lQ3TirWoN4tqszFt5imivMI69r9VDmmkaop6kqyT26RnfEJqi0DV08cQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1439 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The start position for an ins instruction is always encoded as an immediate, so allowing registers to be used by the inline asm makes no sense. It should never happen anyway since a bit index should always be small enough to be treated as an immediate, but remove the nonsensical "r" for sanity. Signed-off-by: Paul Burton --- Changes in v2: None arch/mips/include/asm/bitops.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.= h index 0f5329e32e87..03532ae9f528 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -85,7 +85,7 @@ static inline void set_bit(unsigned long nr, volatile uns= igned long *addr) " " __INS "%0, %3, %2, 1 \n" " " __SC "%0, %1 \n" : "=3D&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m) - : "ir" (bit), "r" (~0) + : "i" (bit), "r" (~0) : __LLSC_CLOBBER); } while (unlikely(!temp)); return; @@ -150,7 +150,7 @@ static inline void clear_bit(unsigned long nr, volatile= unsigned long *addr) " " __INS "%0, $0, %2, 1 \n" " " __SC "%0, %1 \n" : "=3D&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m) - : "ir" (bit) + : "i" (bit) : __LLSC_CLOBBER); } while (unlikely(!temp)); return; @@ -383,7 +383,7 @@ static inline int test_and_clear_bit(unsigned long nr, " " __INS "%0, $0, %3, 1 \n" " " __SC "%0, %1 \n" : "=3D&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=3D&r" (res) - : "ir" (bit) + : "i" (bit) : __LLSC_CLOBBER); } while (unlikely(!temp)); } else { --=20 2.23.0