From: Paul Burton <paul.burton@mips.com>
To: "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
Cc: Huacai Chen <chenhc@lemote.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Paul Burton <pburton@wavecomp.com>
Subject: [PATCH v2 30/36] MIPS: futex: Emit Loongson3 sync workarounds within asm
Date: Tue, 1 Oct 2019 21:53:38 +0000 [thread overview]
Message-ID: <20191001215249.4157062-31-paul.burton@mips.com> (raw)
In-Reply-To: <20191001215249.4157062-1-paul.burton@mips.com>
Generate the sync instructions required to workaround Loongson3 LL/SC
errata within inline asm blocks, which feels a little safer than doing
it from C where strictly speaking the compiler would be well within its
rights to insert a memory access between the separate asm statements we
previously had, containing sync & ll instructions respectively.
Signed-off-by: Paul Burton <paul.burton@mips.com>
---
Changes in v2:
- De-string __WEAK_LLSC_MB to allow its use with __SYNC_ELSE().
arch/mips/include/asm/barrier.h | 13 +++++++------
arch/mips/include/asm/futex.h | 15 +++++++--------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index c7e05e832da9..133afd565067 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -95,13 +95,14 @@ static inline void wmb(void)
* ordering will be done by smp_llsc_mb() and friends.
*/
#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
-#define __WEAK_LLSC_MB " sync \n"
-#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
-#define __LLSC_CLOBBER
+# define __WEAK_LLSC_MB sync
+# define smp_llsc_mb() \
+ __asm__ __volatile__(__stringify(__WEAK_LLSC_MB) : : :"memory")
+# define __LLSC_CLOBBER
#else
-#define __WEAK_LLSC_MB " \n"
-#define smp_llsc_mb() do { } while (0)
-#define __LLSC_CLOBBER "memory"
+# define __WEAK_LLSC_MB
+# define smp_llsc_mb() do { } while (0)
+# define __LLSC_CLOBBER "memory"
#endif
#ifdef CONFIG_CPU_CAVIUM_OCTEON
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index b83b0397462d..54cf20530931 100644
--- a/arch/mips/include/asm/futex.h
+++ b/arch/mips/include/asm/futex.h
@@ -16,6 +16,7 @@
#include <asm/barrier.h>
#include <asm/compiler.h>
#include <asm/errno.h>
+#include <asm/sync.h>
#include <asm/war.h>
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
@@ -32,7 +33,7 @@
" .set arch=r4000 \n" \
"2: sc $1, %2 \n" \
" beqzl $1, 1b \n" \
- __WEAK_LLSC_MB \
+ __stringify(__WEAK_LLSC_MB) \
"3: \n" \
" .insn \n" \
" .set pop \n" \
@@ -50,19 +51,19 @@
"i" (-EFAULT) \
: "memory"); \
} else if (cpu_has_llsc) { \
- loongson_llsc_mb(); \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .set push \n" \
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
+ " " __SYNC(full, loongson3_war) " \n" \
"1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
" .set pop \n" \
" " insn " \n" \
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
"2: "user_sc("$1", "%2")" \n" \
" beqz $1, 1b \n" \
- __WEAK_LLSC_MB \
+ __stringify(__WEAK_LLSC_MB) \
"3: \n" \
" .insn \n" \
" .set pop \n" \
@@ -147,7 +148,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
" .set arch=r4000 \n"
"2: sc $1, %2 \n"
" beqzl $1, 1b \n"
- __WEAK_LLSC_MB
+ __stringify(__WEAK_LLSC_MB)
"3: \n"
" .insn \n"
" .set pop \n"
@@ -164,13 +165,13 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
"i" (-EFAULT)
: "memory");
} else if (cpu_has_llsc) {
- loongson_llsc_mb();
__asm__ __volatile__(
"# futex_atomic_cmpxchg_inatomic \n"
" .set push \n"
" .set noat \n"
" .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
+ " " __SYNC(full, loongson3_war) " \n"
"1: "user_ll("%1", "%3")" \n"
" bne %1, %z4, 3f \n"
" .set pop \n"
@@ -178,8 +179,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
" .set "MIPS_ISA_ARCH_LEVEL" \n"
"2: "user_sc("$1", "%2")" \n"
" beqz $1, 1b \n"
- __WEAK_LLSC_MB
- "3: \n"
+ "3: " __SYNC_ELSE(full, loongson3_war, __WEAK_LLSC_MB) "\n"
" .insn \n"
" .set pop \n"
" .section .fixup,\"ax\" \n"
@@ -194,7 +194,6 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
"i" (-EFAULT)
: "memory");
- loongson_llsc_mb();
} else
return -ENOSYS;
--
2.23.0
next prev parent reply other threads:[~2019-10-01 21:54 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-01 21:53 [PATCH v2 00/36] MIPS: barriers & atomics cleanups Paul Burton
2019-10-01 21:53 ` [PATCH v2 01/36] MIPS: Unify sc beqz definition Paul Burton
2019-10-01 21:53 ` [PATCH v2 02/36] MIPS: Use compact branch for LL/SC loops on MIPSr6+ Paul Burton
2019-10-01 21:53 ` [PATCH v2 03/36] MIPS: barrier: Add __SYNC() infrastructure Paul Burton
2019-10-01 21:53 ` [PATCH v2 04/36] MIPS: barrier: Clean up rmb() & wmb() definitions Paul Burton
2019-10-01 21:53 ` [PATCH v2 05/36] MIPS: barrier: Clean up __smp_mb() definition Paul Burton
2019-10-01 21:53 ` [PATCH v2 06/36] MIPS: barrier: Remove fast_mb() Octeon #ifdef'ery Paul Burton
2019-10-01 21:53 ` [PATCH v2 07/36] MIPS: barrier: Clean up __sync() definition Paul Burton
2019-10-01 21:53 ` [PATCH v2 08/36] MIPS: barrier: Clean up sync_ginv() Paul Burton
2019-10-01 21:53 ` [PATCH v2 09/36] MIPS: atomic: Fix whitespace in ATOMIC_OP macros Paul Burton
2019-10-01 21:53 ` [PATCH v2 10/36] MIPS: atomic: Handle !kernel_uses_llsc first Paul Burton
2019-10-01 21:53 ` [PATCH v2 11/36] MIPS: atomic: Use one macro to generate 32b & 64b functions Paul Burton
2019-10-01 21:53 ` [PATCH v2 12/36] MIPS: atomic: Emit Loongson3 sync workarounds within asm Paul Burton
2019-10-01 21:53 ` [PATCH v2 13/36] MIPS: atomic: Use _atomic barriers in atomic_sub_if_positive() Paul Burton
2019-10-01 21:53 ` [PATCH v2 14/36] MIPS: atomic: Unify 32b & 64b sub_if_positive Paul Burton
2019-10-01 21:53 ` [PATCH v2 15/36] MIPS: atomic: Deduplicate 32b & 64b read, set, xchg, cmpxchg Paul Burton
2019-10-01 21:53 ` [PATCH v2 16/36] MIPS: bitops: Handle !kernel_uses_llsc first Paul Burton
2019-10-01 21:53 ` [PATCH v2 17/36] MIPS: bitops: Only use ins for bit 16 or higher Paul Burton
2019-10-01 21:53 ` [PATCH v2 18/36] MIPS: bitops: Use MIPS_ISA_REV, not #ifdefs Paul Burton
2019-10-01 21:53 ` [PATCH v2 19/36] MIPS: bitops: ins start position is always an immediate Paul Burton
2019-10-01 21:53 ` [PATCH v2 20/36] MIPS: bitops: Implement test_and_set_bit() in terms of _lock variant Paul Burton
2019-10-01 21:53 ` [PATCH v2 21/36] MIPS: bitops: Allow immediates in test_and_{set,clear,change}_bit Paul Burton
2019-10-01 21:53 ` [PATCH v2 22/36] MIPS: bitops: Use the BIT() macro Paul Burton
2019-10-01 21:53 ` [PATCH v2 23/36] MIPS: bitops: Avoid redundant zero-comparison for non-LLSC Paul Burton
2019-10-01 21:53 ` [PATCH v2 24/36] MIPS: bitops: Abstract LL/SC loops Paul Burton
2019-10-01 21:53 ` [PATCH v2 25/36] MIPS: bitops: Use BIT_WORD() & BITS_PER_LONG Paul Burton
2019-10-01 21:53 ` [PATCH v2 26/36] MIPS: bitops: Emit Loongson3 sync workarounds within asm Paul Burton
2019-10-01 21:53 ` [PATCH v2 27/36] MIPS: bitops: Use smp_mb__before_atomic in test_* ops Paul Burton
2019-10-01 21:53 ` [PATCH v2 28/36] MIPS: cmpxchg: Emit Loongson3 sync workarounds within asm Paul Burton
2019-10-01 21:53 ` [PATCH v2 29/36] MIPS: cmpxchg: Omit redundant barriers for Loongson3 Paul Burton
2019-10-01 21:53 ` Paul Burton [this message]
2019-10-01 21:53 ` [PATCH v2 31/36] MIPS: syscall: Emit Loongson3 sync workarounds within asm Paul Burton
2019-10-01 21:53 ` [PATCH v2 32/36] MIPS: barrier: Remove loongson_llsc_mb() Paul Burton
2019-10-01 21:53 ` [PATCH v2 33/36] MIPS: barrier: Make __smp_mb__before_atomic() a no-op for Loongson3 Paul Burton
2019-10-01 21:53 ` [PATCH v2 34/36] MIPS: genex: Add Loongson3 LL/SC workaround to ejtag_debug_handler Paul Burton
2019-10-01 21:53 ` [PATCH v2 35/36] MIPS: genex: Don't reload address unnecessarily Paul Burton
2019-10-01 21:53 ` [PATCH v2 36/36] MIPS: Check Loongson3 LL/SC errata workaround correctness Paul Burton
2019-10-07 17:51 ` [PATCH v2 00/36] MIPS: barriers & atomics cleanups Paul Burton
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