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Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by bombadil.infradead.org with esmtpsa (Exim 4.92.2 #3 (Red Hat Linux)) id 1iHqdY-0007Ki-Hg; Tue, 08 Oct 2019 14:38:52 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 06469305E32; Tue, 8 Oct 2019 16:37:58 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 2F4162020725A; Tue, 8 Oct 2019 16:38:50 +0200 (CEST) Date: Tue, 8 Oct 2019 16:38:50 +0200 From: Peter Zijlstra To: "Liang, Kan" Cc: acme@kernel.org, mingo@kernel.org, linux-kernel@vger.kernel.org, jolsa@kernel.org, namhyung@kernel.org, ak@linux.intel.com, vitaly.slobodskoy@intel.com, pavel.gerasimov@intel.com Subject: Re: [PATCH 01/10] perf/core, x86: Add PERF_SAMPLE_LBR_TOS Message-ID: <20191008143850.GB2328@hirez.programming.kicks-ass.net> References: <20191007175910.2805-1-kan.liang@linux.intel.com> <20191007175910.2805-2-kan.liang@linux.intel.com> <20191008083141.GH2294@hirez.programming.kicks-ass.net> <3ac026c3-6b9c-a6c1-2c2b-c7ecdbb22b1d@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3ac026c3-6b9c-a6c1-2c2b-c7ecdbb22b1d@linux.intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 08, 2019 at 09:53:24AM -0400, Liang, Kan wrote: > > > On 10/8/2019 4:31 AM, Peter Zijlstra wrote: > > On Mon, Oct 07, 2019 at 10:59:01AM -0700, kan.liang@linux.intel.com wrote: > > > diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h > > > index 61448c19a132..ee9ef0c4cb08 100644 > > > --- a/include/linux/perf_event.h > > > +++ b/include/linux/perf_event.h > > > @@ -100,6 +100,7 @@ struct perf_raw_record { > > > */ > > > struct perf_branch_stack { > > > __u64 nr; > > > + __u64 tos; > > > struct perf_branch_entry entries[0]; > > > }; > > > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h > > > index bb7b271397a6..fe36ebb7dc2e 100644 > > > --- a/include/uapi/linux/perf_event.h > > > +++ b/include/uapi/linux/perf_event.h > > > @@ -141,8 +141,9 @@ enum perf_event_sample_format { > > > PERF_SAMPLE_TRANSACTION = 1U << 17, > > > PERF_SAMPLE_REGS_INTR = 1U << 18, > > > PERF_SAMPLE_PHYS_ADDR = 1U << 19, > > > + PERF_SAMPLE_LBR_TOS = 1U << 20, > > > - PERF_SAMPLE_MAX = 1U << 20, /* non-ABI */ > > > + PERF_SAMPLE_MAX = 1U << 21, /* non-ABI */ > > > __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ > > > }; > > > @@ -864,6 +865,7 @@ enum perf_event_type { > > > * { u64 abi; # enum perf_sample_regs_abi > > > * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR > > > * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR > > > + * { u64 tos;} && PERF_SAMPLE_LBR_TOS > > > * }; > > > */ > > > PERF_RECORD_SAMPLE = 9, > > > > I have problems with the API.. You're introducing the intel specific LBR > > naming, and adding a whole new sample type vs extending the existing > > BRANCH_STACK (like you really already do with struct perf_branch_stack). > > > So why not add a bit to PERF_SAMPLE_BRANCH_* to request the presence of > > the TOS field in the PERF_SAMPLE_BRANCH_STACK output? > > We never store PERF_SAMPLE_BRANCH_* in a sample. The perf tool cannot tell > if the sample includes TOS field. The perf tool bloody sets the perf_event_attr::branch_sample_type value! Of course it knows to expect the TOS field when it asks for it in the first place. > There will be a problem when a new perf tool parsing the data generated by > an old kernel. ISTR perf stores the full perf_event_attr in the .data file these days, and therefore such confusion should never happen.