From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9A6DECE587 for ; Mon, 14 Oct 2019 09:23:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7F3FF20659 for ; Mon, 14 Oct 2019 09:23:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="IFqMGZb+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730844AbfJNJXm (ORCPT ); Mon, 14 Oct 2019 05:23:42 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:24986 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730676AbfJNJXm (ORCPT ); Mon, 14 Oct 2019 05:23:42 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9E9Biq9022257; Mon, 14 Oct 2019 11:23:19 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=STMicroelectronics; bh=gEmBsIEorhGPSpDkFEP6FJmifXJuypR7WyitQNE9F3U=; b=IFqMGZb+TTWAv7lhNQiinPV3XsSxyxdw6e/u3hIocGh75+SUDJ52xgajrfxq2PIxOZ9T O/U6R+Jk1PL8X2a1Kxh476tABtb5XWgeTuzzMLOjTWKqWFgF13XVn6vSP01kvLgxkbav 2el7XkOb22YokGc/v7MlbkVdH6c8JdVperl5hlEvgPqbGv/zUAY1P1cxdzoKUmIiwOp4 nm+m8Z0ld5DRzlauPqP7gJ13kRXhUzZBfOcy/e8JTmNn4MvsHcm5cEDH2dFyazqlBDSn gquyoiW7aRZhBEmlakpzjvIYpxaF/tgEROKMNBbwAsjDy3bPYnW2iyZMZ3Kkfs/k+/Lr BA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2vk3y9hshw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 14 Oct 2019 11:23:19 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B2A6510002A; Mon, 14 Oct 2019 11:23:18 +0200 (CEST) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A2F032B189A; Mon, 14 Oct 2019 11:23:18 +0200 (CEST) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 14 Oct 2019 11:23:18 +0200 Received: from localhost (10.201.20.122) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 14 Oct 2019 11:23:18 +0200 From: Benjamin Gaignard To: , , , CC: , , , , Benjamin Gaignard Subject: [PATCH v3] dt-bindings: timer: Convert stm32 timer bindings to json-schema Date: Mon, 14 Oct 2019 11:23:16 +0200 Message-ID: <20191014092316.24337-1-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.20.122] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-14_06:2019-10-10,2019-10-14 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the STM32 timer binding to DT schema format using json-schema Signed-off-by: Benjamin Gaignard --- changes in v3: - use (GPL-2.0-only OR BSD-2-Clause) license - fix identation - add additionalProperties: false .../devicetree/bindings/timer/st,stm32-timer.txt | 22 ---------- .../devicetree/bindings/timer/st,stm32-timer.yaml | 47 ++++++++++++++++++++++ 2 files changed, 47 insertions(+), 22 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/st,stm32-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/st,stm32-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/st,stm32-timer.txt b/Documentation/devicetree/bindings/timer/st,stm32-timer.txt deleted file mode 100644 index 8ef28e70d6e8..000000000000 --- a/Documentation/devicetree/bindings/timer/st,stm32-timer.txt +++ /dev/null @@ -1,22 +0,0 @@ -. STMicroelectronics STM32 timer - -The STM32 MCUs family has several general-purpose 16 and 32 bits timers. - -Required properties: -- compatible : Should be "st,stm32-timer" -- reg : Address and length of the register set -- clocks : Reference on the timer input clock -- interrupts : Reference to the timer interrupt - -Optional properties: -- resets: Reference to a reset controller asserting the timer - -Example: - -timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - resets = <&rrc 259>; - clocks = <&clk_pmtr1>; -}; diff --git a/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml b/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml new file mode 100644 index 000000000000..176aa3c9baf8 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/st,stm32-timer.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/st,stm32-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 general-purpose 16 and 32 bits timers bindings + +maintainers: + - Benjamin Gaignard + +properties: + compatible: + const: st,stm32-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + timer: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&clk_pmtr1>; + }; + +... -- 2.15.0