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Wed, 16 Oct 2019 16:12:13 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K CC: Daniel Lezcano , Thomas Gleixner , Alexander Graf , Atish Patra , Alistair Francis , Damien Le Moal , Christoph Hellwig , Anup Patel , "kvm@vger.kernel.org" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Anup Patel Subject: [PATCH v9 20/22] RISC-V: KVM: Fix race-condition in kvm_riscv_vcpu_sync_interrupts() Thread-Topic: [PATCH v9 20/22] RISC-V: KVM: Fix race-condition in kvm_riscv_vcpu_sync_interrupts() Thread-Index: AQHVhDx46fm8fRcOYUC/zsYHJwPs5w== Date: Wed, 16 Oct 2019 16:12:12 +0000 Message-ID: <20191016160649.24622-21-anup.patel@wdc.com> References: <20191016160649.24622-1-anup.patel@wdc.com> In-Reply-To: <20191016160649.24622-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MAXPR01CA0098.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:5d::16) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; 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x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: xY6lIG39DZpGdfVN6dkQcJiI/lrv569kkdsinnj+mrPSfkrQj3SPbcCPnNZzBErPgKaxvICRtd96QQZSHV46Q58O1FkuA0DknH3VAC0h+KJpVoK1ar2qPt9Gb6MMJqLF+J8zXPi5yWLPB7QeK547GJeIaqxT4IjmQ50H/JlkgrJVXAxxFt/4Z/ND5yYaWJw5ZCMQHLf/7shcsx02cOLyyl/BY+jyuLe2cUm0zihs0siaC0K1EMOGPnuxJHmmwjCWHD3B2sXwhVrZU8dm7yjfMVkUseO3t+83u43sQFdbPieqvuTHRJocnZoOdKcrOuS5bv1J9RSALfP4O8bG7ZyV/1iYZFtxSuhLa9Veuc8RUx1wcVhd564uPjLCW/eSX2R4CdYnu0fqp7YiBZ0ZXcYlpA8DsgtovaYp+RYf3KVtmtQ= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 807ae80b-09ee-42f8-17c1-08d752539aaf X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Oct 2019 16:12:12.9492 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JsVsfRIYr/YkfitTZKva6aUMjlXbWFDCvk+U8LIQnnWDLPU7iM37qHX28vqHmngFu4Syx/qeyyUwrHuXqvLAuA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6397 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently, we sync-up Guest VSIP and VSIE CSRs with HW state upon VM-exit. This helps us track enable/disable state of interrupts and VSIP.SSIP bit updates by Guest. Unfortunately, the implementation of kvm_riscv_vcpu_sync_interrupts() is racey when running SMP Guest on SMP Host because it can happen that IRQ_S_SOFT is already queued from other Host CPU and we might accidentally clear a valid pending IRQ_S_SOFT. To fix this, we use test_and_set_bit() to update irqs_pending_mask in kvm_riscv_vcpu_sync_interrupts() instead of directly calling kvm_riscv_vcpu_set/unset_interrupt() functions. Signed-off-by: Anup Patel --- arch/riscv/kvm/vcpu.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index f1a218d3a8cf..844542dd13e4 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -662,15 +662,22 @@ void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu = *vcpu) =20 void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) { - vcpu->arch.guest_csr.vsip =3D csr_read(CSR_VSIP); - vcpu->arch.guest_csr.vsie =3D csr_read(CSR_VSIE); + unsigned long vsip; + struct kvm_vcpu_arch *v =3D &vcpu->arch; + struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; =20 - /* Guest can directly update VSIP software interrupt bits */ - if (vcpu->arch.guest_csr.vsip ^ READ_ONCE(vcpu->arch.irqs_pending)) { - if (vcpu->arch.guest_csr.vsip & (1UL << IRQ_S_SOFT)) - kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_S_SOFT); - else - kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_S_SOFT); + /* Read current VSIP and VSIE CSRs */ + vsip =3D csr_read(CSR_VSIP); + csr->vsie =3D csr_read(CSR_VSIE); + + /* Sync-up VSIP.SSIP bit changes does by Guest */ + if ((csr->vsip ^ vsip) & (1UL << IRQ_S_SOFT)) { + if (!test_and_set_bit(IRQ_S_SOFT, &v->irqs_pending_mask)) { + if (vsip & (1UL << IRQ_S_SOFT)) + set_bit(IRQ_S_SOFT, &v->irqs_pending); + else + clear_bit(IRQ_S_SOFT, &v->irqs_pending); + } } } =20 --=20 2.17.1