From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD08DFA372A for ; Thu, 17 Oct 2019 17:38:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A5F6B21925 for ; Thu, 17 Oct 2019 17:38:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="TneWA4PI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2503103AbfJQRiJ (ORCPT ); Thu, 17 Oct 2019 13:38:09 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:36550 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2503091AbfJQRiI (ORCPT ); Thu, 17 Oct 2019 13:38:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From :Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=KV+3P0fQpSURBvq8mXZB/BbmVusxMF9n6NvORxQIaL0=; b=TneWA4PI6QhRDu/Rjg5XIBha5y VlNF/fz3aEbQlL9c8gyi0tu7envsClIpXywt/Y5pQE5CiCiJrRS1nT2IIlxS1xEiYU3lJ4mLC4riB n5w3rlltP4KyOsbj+J66iESsUOTD8uPbo78F8pgIvVIu0blNKHqbVSUD5Is2uJ8ACvZWUNFxYXzL3 JBSFWc8eB0v2995tZJIqTVn0TSvuF3FU/xTW2XAkQ7BsD0kXsTTAqMYtbfe7ptfxlCq/VZoQAuA9V xgL/9U8buuwm76CNspjQnSXGKYUXxcWGUKmoxOhjFpwXqRbLqT44ZFuHC0dYlvv8AXUmJxbC/cKBw QgB7Uwlw==; Received: from [2001:4bb8:18c:d7b:c70:4a89:bc61:3] (helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1iL9iv-0007m2-Od; Thu, 17 Oct 2019 17:38:06 +0000 From: Christoph Hellwig To: Palmer Dabbelt , Paul Walmsley Cc: Damien Le Moal , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/15] riscv: add support for MMIO access to the timer registers Date: Thu, 17 Oct 2019 19:37:36 +0200 Message-Id: <20191017173743.5430-9-hch@lst.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191017173743.5430-1-hch@lst.de> References: <20191017173743.5430-1-hch@lst.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When running in M-mode we can't use the SBI to set the timer, and don't have access to the time CSR as that usually is emulated by M-mode. Instead provide code that directly accesses the MMIO for the timer. Signed-off-by: Christoph Hellwig --- arch/riscv/include/asm/sbi.h | 3 ++- arch/riscv/include/asm/timex.h | 19 +++++++++++++++++-- drivers/clocksource/timer-riscv.c | 21 +++++++++++++++++---- 3 files changed, 36 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 0cb74eccc73f..a4774bafe033 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -95,7 +95,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid); } #else /* CONFIG_RISCV_SBI */ -/* stub to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */ +/* stubs to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */ +void sbi_set_timer(uint64_t stime_value); void sbi_remote_fence_i(const unsigned long *hart_mask); #endif /* CONFIG_RISCV_SBI */ #endif /* _ASM_RISCV_SBI_H */ diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h index c7ef131b9e4c..e17837d61667 100644 --- a/arch/riscv/include/asm/timex.h +++ b/arch/riscv/include/asm/timex.h @@ -7,12 +7,25 @@ #define _ASM_RISCV_TIMEX_H #include +#include typedef unsigned long cycles_t; +extern u64 __iomem *riscv_time_val; +extern u64 __iomem *riscv_time_cmp; + +#ifdef CONFIG_64BIT +#define mmio_get_cycles() readq_relaxed(riscv_time_val) +#else +#define mmio_get_cycles() readl_relaxed(riscv_time_val) +#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1) +#endif + static inline cycles_t get_cycles(void) { - return csr_read(CSR_TIME); + if (IS_ENABLED(CONFIG_RISCV_SBI)) + return csr_read(CSR_TIME); + return mmio_get_cycles(); } #define get_cycles get_cycles @@ -24,7 +37,9 @@ static inline u64 get_cycles64(void) #else /* CONFIG_64BIT */ static inline u32 get_cycles_hi(void) { - return csr_read(CSR_TIMEH); + if (IS_ENABLED(CONFIG_RISCV_SBI)) + return csr_read(CSR_TIMEH); + return mmio_get_cycles_hi(); } static inline u64 get_cycles64(void) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 5d2fdc3e28a9..2b9fbc4ebe49 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -3,9 +3,9 @@ * Copyright (C) 2012 Regents of the University of California * Copyright (C) 2017 SiFive * - * All RISC-V systems have a timer attached to every hart. These timers can be - * read from the "time" and "timeh" CSRs, and can use the SBI to setup - * events. + * All RISC-V systems have a timer attached to every hart. These timers can + * either be read from the "time" and "timeh" CSRs, and can use the SBI to + * setup events, or directly accessed using MMIO registers. */ #include #include @@ -13,14 +13,27 @@ #include #include #include +#include #include #include +u64 __iomem *riscv_time_cmp; +u64 __iomem *riscv_time_val; + +static inline void mmio_set_timer(u64 val) +{ + writeq_relaxed(val, + riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id())); +} + static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { csr_set(CSR_XIE, XIE_XTIE); - sbi_set_timer(get_cycles64() + delta); + if (IS_ENABLED(CONFIG_RISCV_SBI)) + sbi_set_timer(get_cycles64() + delta); + else + mmio_set_timer(get_cycles64() + delta); return 0; } -- 2.20.1