From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A9D0CA9EA0 for ; Fri, 18 Oct 2019 11:05:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F175C2064B for ; Fri, 18 Oct 2019 11:05:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2409900AbfJRLFX (ORCPT ); Fri, 18 Oct 2019 07:05:23 -0400 Received: from [217.140.110.172] ([217.140.110.172]:35192 "EHLO foss.arm.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S2406290AbfJRLFW (ORCPT ); Fri, 18 Oct 2019 07:05:22 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 119BEAB6; Fri, 18 Oct 2019 04:04:57 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2AB4E3F6C4; Fri, 18 Oct 2019 04:04:54 -0700 (PDT) Date: Fri, 18 Oct 2019 12:04:29 +0100 From: Mark Rutland To: Dave Martin Cc: Paul Elliott , Peter Zijlstra , Catalin Marinas , Will Deacon , Yu-cheng Yu , Amit Kachhap , Vincenzo Frascino , linux-arch@vger.kernel.org, Eugene Syromiatnikov , Szabolcs Nagy , "H.J. Lu" , Andrew Jones , Kees Cook , Arnd Bergmann , Jann Horn , Richard Henderson , Kristina =?utf-8?Q?Mart=C5=A1enko?= , Mark Brown , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Florian Weimer , linux-kernel@vger.kernel.org, Sudakshina Das Subject: Re: [PATCH v2 11/12] arm64: BTI: Reset BTYPE when skipping emulated instructions Message-ID: <20191018110428.GA27759@lakrids.cambridge.arm.com> References: <1570733080-21015-1-git-send-email-Dave.Martin@arm.com> <1570733080-21015-12-git-send-email-Dave.Martin@arm.com> <20191011142157.GC33537@lakrids.cambridge.arm.com> <20191011144743.GJ27757@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191011144743.GJ27757@arm.com> User-Agent: Mutt/1.11.1+11 (2f07cb52) (2018-12-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 11, 2019 at 03:47:43PM +0100, Dave Martin wrote: > On Fri, Oct 11, 2019 at 03:21:58PM +0100, Mark Rutland wrote: > > On Thu, Oct 10, 2019 at 07:44:39PM +0100, Dave Martin wrote: > > > Since normal execution of any non-branch instruction resets the > > > PSTATE BTYPE field to 0, so do the same thing when emulating a > > > trapped instruction. > > > > > > Branches don't trap directly, so we should never need to assign a > > > non-zero value to BTYPE here. > > > > > > Signed-off-by: Dave Martin > > > --- > > > arch/arm64/kernel/traps.c | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > > > index 3af2768..4d8ce50 100644 > > > --- a/arch/arm64/kernel/traps.c > > > +++ b/arch/arm64/kernel/traps.c > > > @@ -331,6 +331,8 @@ void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) > > > > > > if (regs->pstate & PSR_MODE32_BIT) > > > advance_itstate(regs); > > > + else > > > + regs->pstate &= ~(u64)PSR_BTYPE_MASK; > > > > This looks good to me, with one nit below. > > > > We don't (currently) need the u64 cast here, and it's inconsistent with > > what we do elsewhere. If the upper 32-bit of pstate get allocated, we'll > > need to fix up all the other masking we do: > > Huh, looks like I missed that. Dang. Will fix. > > > [mark@lakrids:~/src/linux]% git grep 'pstate &= ~' > > arch/arm64/kernel/armv8_deprecated.c: regs->pstate &= ~PSR_AA32_E_BIT; > > arch/arm64/kernel/cpufeature.c: regs->pstate &= ~PSR_SSBS_BIT; > > arch/arm64/kernel/debug-monitors.c: regs->pstate &= ~DBG_SPSR_SS; > > arch/arm64/kernel/insn.c: pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ > > arch/arm64/kernel/insn.c: pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ > > arch/arm64/kernel/probes/kprobes.c: regs->pstate &= ~PSR_D_BIT; > > arch/arm64/kernel/probes/kprobes.c: regs->pstate &= ~DAIF_MASK; > > arch/arm64/kernel/ptrace.c: regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS; > > arch/arm64/kernel/ptrace.c: regs->pstate &= ~PSR_AA32_E_BIT; > > arch/arm64/kernel/ptrace.c: regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS; > > arch/arm64/kernel/ptrace.c: regs->pstate &= ~DBG_SPSR_SS; > > arch/arm64/kernel/ssbd.c: task_pt_regs(task)->pstate &= ~val; > > arch/arm64/kernel/traps.c: regs->pstate &= ~PSR_AA32_IT_MASK; > > > > ... and at that point I'd suggest we should just ensure the bit > > definitions are all defined as unsigned long in the first place since > > adding casts to each use is error-prone. > > Are we concerned about changing the types of UAPI #defines? That can > cause subtle and unexpected breakage, especially when the signedness > of a #define changes. > > Ideally, we'd just change all these to 1UL << n. I agree that's the ideal -- I don't know how concerned we are w.r.t. the UAPI headers, I'm afraid. Thanks, Mark.