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From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: acme@kernel.org, mingo@kernel.org, linux-kernel@vger.kernel.org,
	jolsa@kernel.org, namhyung@kernel.org,
	vitaly.slobodskoy@intel.com, pavel.gerasimov@intel.com,
	ak@linux.intel.com, eranian@google.com
Subject: Re: [PATCH V2 01/13] perf/core: Add new branch sample type for LBR TOS
Date: Tue, 22 Oct 2019 11:39:26 +0200	[thread overview]
Message-ID: <20191022093926.GH1800@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20191021200314.1613-2-kan.liang@linux.intel.com>

On Mon, Oct 21, 2019 at 01:03:02PM -0700, kan.liang@linux.intel.com wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
> 
> In LBR call stack mode, the depth of reconstructed LBR call stack limits
> to the number of LBR registers. With LBR Top-of-Stack (TOS) information,
> perf tool may stitch the stacks of two samples. The reconstructed LBR
> call stack can break the HW limitation.
> 
> Add a new branch sample type to retrieve LBR TOS.
> 
> Only when the new branch sample type is set, the TOS information is
> dumped into the PERF_SAMPLE_BRANCH_STACK output.
> Perf tool should check the attr.branch_sample_type, and apply the
> corresponding format for PERF_SAMPLE_BRANCH_STACK samples.
> Otherwise, some user case may be broken. For example, users may parse a
> perf.data, which include the new branch sample type, with an old version
> perf tool (without the check). Users probably get incorrect information
> without any warning.
> 
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> ---
>  include/linux/perf_event.h      |  4 ++++
>  include/uapi/linux/perf_event.h | 10 +++++++++-
>  kernel/events/core.c            | 10 ++++++++++
>  3 files changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
> index 61448c19a132..0cebc8ec44fa 100644
> --- a/include/linux/perf_event.h
> +++ b/include/linux/perf_event.h
> @@ -972,6 +972,10 @@ struct perf_sample_data {
>  	u64				stack_user_size;
>  
>  	u64				phys_addr;
> +
> +	/* PMU specific data */
> +	u64				lbr_tos;
> +
>  } ____cacheline_aligned;

Last time you put this in perf_branch_stack, that was a much better
place. Can't this work now?

  reply	other threads:[~2019-10-22  9:39 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-21 20:03 [PATCH V2 00/13] Stitch LBR call stack kan.liang
2019-10-21 20:03 ` [PATCH V2 01/13] perf/core: Add new branch sample type for LBR TOS kan.liang
2019-10-22  9:39   ` Peter Zijlstra [this message]
2019-10-22 15:39     ` Liang, Kan
2019-10-21 20:03 ` [PATCH V2 02/13] perf/x86/intel: Output LBR TOS information kan.liang
2019-10-21 20:03 ` [PATCH V2 03/13] perf tools: Support new branch sample type for LBR TOS kan.liang
2019-10-21 20:03 ` [PATCH V2 04/13] perf header: Add check for event attr kan.liang
2019-10-21 20:03 ` [PATCH V2 05/13] perf pmu: Add support for PMU capabilities kan.liang
2019-10-21 20:03 ` [PATCH V2 06/13] perf header: Support CPU " kan.liang
2019-10-21 20:03 ` [PATCH V2 07/13] perf machine: Refine the function for LBR call stack reconstruction kan.liang
2019-10-21 20:03 ` [PATCH V2 08/13] perf tools: Stitch LBR call stack kan.liang
2019-10-21 20:03 ` [PATCH V2 09/13] perf report: Add option to enable the LBR stitching approach kan.liang
2019-10-21 20:03 ` [PATCH V2 10/13] perf script: " kan.liang
2019-10-21 20:03 ` [PATCH V2 11/13] perf top: " kan.liang
2019-10-21 20:03 ` [PATCH V2 12/13] perf c2c: " kan.liang
2019-10-21 20:03 ` [RFC PATCH V2 13/13] perf hist: Add fast path for duplicate entries check kan.liang

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