From: Tony Luck <tony.luck@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Tony Luck <tony.luck@intel.com>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH] x86/mce: Add Xeon Icelake to list of CPUs that support PPIN
Date: Mon, 28 Oct 2019 09:37:19 -0700 [thread overview]
Message-ID: <20191028163719.19708-1-tony.luck@intel.com> (raw)
New CPU model, same MSRs to control and read the inventory number.
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
arch/x86/kernel/cpu/mce/intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 88cd9598fa57..c2ffe098420a 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -482,6 +482,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
case INTEL_FAM6_BROADWELL_D:
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SKYLAKE_X:
+ case INTEL_FAM6_ICELAKE_X:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM:
--
2.20.1
next reply other threads:[~2019-10-28 16:37 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 16:37 Tony Luck [this message]
2019-11-01 16:37 ` [tip: ras/core] " tip-bot2 for Tony Luck
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