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Tue, 29 Oct 2019 11:17:04 +0000 From: To: , , , CC: , , Subject: [PATCH v3 10/32] mtd: spi-nor: Pointer parameter for CR in spi_nor_read_cr() Thread-Topic: [PATCH v3 10/32] mtd: spi-nor: Pointer parameter for CR in spi_nor_read_cr() Thread-Index: AQHVjkpkiF1slcDF2Ua4XfvPGlZW3A== Date: Tue, 29 Oct 2019 11:17:04 +0000 Message-ID: <20191029111615.3706-11-tudor.ambarus@microchip.com> References: <20191029111615.3706-1-tudor.ambarus@microchip.com> In-Reply-To: <20191029111615.3706-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LO2P265CA0376.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a3::28) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [83.166.207.93] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 92b74673-8c52-4f0a-956b-08d75c6186dc x-ms-traffictypediagnostic: MN2PR11MB3823: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6790; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 92b74673-8c52-4f0a-956b-08d75c6186dc X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2019 11:17:04.2099 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: FI2dBaw3YtY5l87HL9fmEvM/7B70wyw7eHNwaHzvzbbznGaTUdYbNaznbbP7H8q1g5kyNIDwMraeB2PPE6eVw3FoiwZCtiqDY22wYn4m9lI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3823 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Let the callers pass the pointer to the DMA-able buffer where the value of the Configuration Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_cr() with negative, spi_nor_read_cr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 55 +++++++++++++++++++++++----------------= ---- 1 file changed, 30 insertions(+), 25 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 0d38aede4de7..ec179eac2069 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -487,12 +487,16 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *= fsr) return ret; } =20 -/* - * Read configuration register, returning its value in the - * location. Return the configuration register value. - * Returns negative if error occurred. +/** + * spi_nor_read_cr() - Read the Configuration Register using the + * SPINOR_OP_RDCR (35h) command. + * @nor: pointer to 'struct spi_nor' + * @cr: pointer to a DMA-able buffer where the value of the + * Configuration Register will be written. + * + * Return: 0 on success, -errno otherwise. */ -static int spi_nor_read_cr(struct spi_nor *nor) +static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) { int ret; =20 @@ -501,20 +505,17 @@ static int spi_nor_read_cr(struct spi_nor *nor) SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 1), SPI_MEM_OP_NO_ADDR, SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1)); + SPI_MEM_OP_DATA_IN(1, cr, 1)); =20 ret =3D spi_mem_exec_op(nor->spimem, &op); } else { - ret =3D nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, - nor->bouncebuf, 1); + ret =3D nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1); } =20 - if (ret) { + if (ret) dev_err(nor->dev, "error %d reading CR\n", ret); - return ret; - } =20 - return nor->bouncebuf[0]; + return ret; } =20 /* @@ -1820,8 +1821,11 @@ static int spansion_quad_enable(struct spi_nor *nor) return ret; =20 /* read back and check it */ - ret =3D spi_nor_read_cr(nor); - if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { + ret =3D spi_nor_read_cr(nor, &nor->bouncebuf[0]); + if (ret) + return ret; + + if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) { dev_err(nor->dev, "Spansion Quad bit not set\n"); return -EINVAL; } @@ -1879,16 +1883,16 @@ static int spansion_read_cr_quad_enable(struct spi_= nor *nor) int ret; =20 /* Check current Quad Enable bit value. */ - ret =3D spi_nor_read_cr(nor); - if (ret < 0) { + ret =3D spi_nor_read_cr(nor, &sr_cr[1]); + if (ret) { dev_err(dev, "error while reading configuration register\n"); return ret; } =20 - if (ret & CR_QUAD_EN_SPAN) + if (sr_cr[1] & CR_QUAD_EN_SPAN) return 0; =20 - sr_cr[1] =3D ret | CR_QUAD_EN_SPAN; + sr_cr[1] |=3D CR_QUAD_EN_SPAN; =20 /* Keep the current value of the Status Register. */ ret =3D spi_nor_read_sr(nor, &sr_cr[0]); @@ -1902,8 +1906,11 @@ static int spansion_read_cr_quad_enable(struct spi_n= or *nor) return ret; =20 /* Read back and check it. */ - ret =3D spi_nor_read_cr(nor); - if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { + ret =3D spi_nor_read_cr(nor, &sr_cr[1]); + if (ret) + return ret; + + if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) { dev_err(nor->dev, "Spansion Quad bit not set\n"); return -EINVAL; } @@ -2019,8 +2026,8 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_no= r *nor) u8 *sr_cr =3D nor->bouncebuf; =20 /* Check current Quad Enable bit value. */ - ret =3D spi_nor_read_cr(nor); - if (ret < 0) { + ret =3D spi_nor_read_cr(nor, &sr_cr[1]); + if (ret) { dev_err(nor->dev, "error while reading configuration register\n"); return ret; @@ -2030,9 +2037,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_no= r *nor) * When the configuration register Quad Enable bit is one, only the * Write Status (01h) command with two data bytes may be used. */ - if (ret & CR_QUAD_EN_SPAN) { - sr_cr[1] =3D ret; - + if (sr_cr[1] & CR_QUAD_EN_SPAN) { ret =3D spi_nor_read_sr(nor, &sr_cr[0]); if (ret) { dev_err(nor->dev, --=20 2.9.5