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Tue, 29 Oct 2019 11:17:15 +0000 From: To: , , , CC: , , Subject: [PATCH v3 17/32] mtd: spi-nor: Move the WE and wait calls inside Write SR methods Thread-Topic: [PATCH v3 17/32] mtd: spi-nor: Move the WE and wait calls inside Write SR methods Thread-Index: AQHVjkpr8F0rwzTvmE6TWCmKgh0hVg== Date: Tue, 29 Oct 2019 11:17:15 +0000 Message-ID: <20191029111615.3706-18-tudor.ambarus@microchip.com> References: <20191029111615.3706-1-tudor.ambarus@microchip.com> In-Reply-To: <20191029111615.3706-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LO2P265CA0376.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a3::28) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [83.166.207.93] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 66ba775e-e377-4339-89b1-08d75c618da7 x-ms-traffictypediagnostic: MN2PR11MB3712: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3173; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 66ba775e-e377-4339-89b1-08d75c618da7 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2019 11:17:15.6243 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3BIo1XAcol59MrTeKMhTzJN4fUY1IGG/eP6h1ZREJ8OHMi6c1z2Uj2n2W5exDcOeaZKaVNKIyLpRGxs2eqB/W1TJxgHnQ9ZUaUcq4LxyuZI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3712 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Avoid duplicating code by moving the calls to spi_nor_write_enable() and spi_nor_wait_till_ready() inside the Write Status Register methods. Move spi_nor_write_sr() to avoid forward declaration of spi_nor_wait_till_ready(). Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 108 +++++++++++++++++---------------------= ---- 1 file changed, 44 insertions(+), 64 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index ed7c233a7208..5fb4d953b5c7 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -534,35 +534,6 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr= ) return ret; } =20 -/* - * Write status register 1 byte - * Returns negative if error occurred. - */ -static int spi_nor_write_sr(struct spi_nor *nor, u8 val) -{ - int ret; - - nor->bouncebuf[0] =3D val; - if (nor->spimem) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR, - nor->bouncebuf, 1); - } - - if (ret) - dev_err(nor->dev, "error %d writing SR\n", ret); - - return ret; - -} - static int macronix_set_4byte(struct spi_nor *nor, bool enable) { int ret; @@ -854,6 +825,41 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor= ) } =20 /* + * Write status register 1 byte + * Returns negative if error occurred. + */ +static int spi_nor_write_sr(struct spi_nor *nor, u8 val) +{ + int ret; + + nor->bouncebuf[0] =3D val; + + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + + if (nor->spimem) { + struct spi_mem_op op =3D + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR, + nor->bouncebuf, 1); + } + + if (ret) { + dev_err(nor->dev, "error %d writing SR\n", ret); + return ret; + } + + return spi_nor_wait_till_ready(nor); +} + +/* * Write status Register and configuration register with 2 bytes * The first byte will be written to the status register, while the * second byte will be written to the configuration register. @@ -895,18 +901,10 @@ static int spi_nor_write_sr_and_check(struct spi_nor = *nor, u8 status_new, { int ret; =20 - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - ret =3D spi_nor_write_sr(nor, status_new); if (ret) return ret; =20 - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; - ret =3D spi_nor_read_sr(nor, &nor->bouncebuf[0]); if (ret) return ret; @@ -918,6 +916,10 @@ static int spi_nor_write_sr2(struct spi_nor *nor, u8 *= sr2) { int ret; =20 + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + if (nor->spimem) { struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1), @@ -931,10 +933,12 @@ static int spi_nor_write_sr2(struct spi_nor *nor, u8 = *sr2) sr2, 1); } =20 - if (ret) + if (ret) { dev_err(nor->dev, "error %d writing SR2\n", ret); + return ret; + } =20 - return ret; + return spi_nor_wait_till_ready(nor); } =20 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) @@ -1864,18 +1868,10 @@ static int macronix_quad_enable(struct spi_nor *nor= ) if (nor->bouncebuf[0] & SR_QUAD_EN_MX) return 0; =20 - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - ret =3D spi_nor_write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX); if (ret) return ret; =20 - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; - ret =3D spi_nor_read_sr(nor, &nor->bouncebuf[0]); if (ret) return ret; @@ -2041,18 +2037,10 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor= ) /* Update the Quad Enable bit. */ *sr2 |=3D SR2_QUAD_EN_BIT7; =20 - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - ret =3D spi_nor_write_sr2(nor, sr2); if (ret) return ret; =20 - ret =3D spi_nor_wait_till_ready(nor); - if (ret) - return ret; - /* Read back and check it. */ ret =3D spi_nor_read_sr2(nor, sr2); if (ret) @@ -2084,15 +2072,7 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) if (ret) return ret; =20 - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - - ret =3D spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask); - if (ret) - return ret; - - return spi_nor_wait_till_ready(nor); + return spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask); } =20 /** --=20 2.9.5