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Tue, 29 Oct 2019 11:17:35 +0000 From: To: , , , CC: , , Subject: [PATCH v3 29/32] mtd: spi-nor: Merge spansion Quad Enable methods Thread-Topic: [PATCH v3 29/32] mtd: spi-nor: Merge spansion Quad Enable methods Thread-Index: AQHVjkp3lnwsMoAClkS5KjFD3sxgZQ== Date: Tue, 29 Oct 2019 11:17:35 +0000 Message-ID: <20191029111615.3706-30-tudor.ambarus@microchip.com> References: <20191029111615.3706-1-tudor.ambarus@microchip.com> In-Reply-To: <20191029111615.3706-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LO2P265CA0376.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a3::28) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [83.166.207.93] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 4d2517e6-c5e4-4c3b-01fe-08d75c619990 x-ms-traffictypediagnostic: MN2PR11MB3712: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 4d2517e6-c5e4-4c3b-01fe-08d75c619990 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2019 11:17:35.6028 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: N6dacZyPpHraXwU6MRbUZehwBOfidE5vCi09jAVJtKYmm6aJ+kUx7B8YNJpl2CQkYXbFRG5TtQ+eL7V5HXhdYeHWqkpjN19fMjBJOLhHsow= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3712 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Merge spansion_no_read_cr_quad_enable() spansion_read_cr_quad_enable() into spi_nor_sr2_bit1_quad_enable(). Reduce code duplication by introducing spi_nor_write_16bit_cr_and_check(). The Configuration Register contains bits that can be updated in future: FREEZE, CMP. Provide a generic method that allows updating all bits of the Configuration Register. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 165 +++++++++++++++++---------------------= ---- 1 file changed, 68 insertions(+), 97 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 1f7ccd80b8ed..ab028afc503f 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1055,6 +1055,59 @@ static int spi_nor_write_16bit_sr_and_check(struct s= pi_nor *nor, u8 sr1) } =20 /** + * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and th= e + * Configuration Register in one shot. Ensure that the byte written in the + * Configuration Register match the received value, and that the 16-bit Wr= ite + * did not affect what was already in the Status Register 1. + * @nor: pointer to a 'struct spi_nor'. + * @cr: byte value to be written to the Configuration Register. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr) +{ + int ret; + u8 *sr_cr =3D nor->bouncebuf; + u8 sr_written; + + /* Keep the current value of the Status Register 1. */ + ret =3D spi_nor_read_sr(nor, &sr_cr[0]); + if (ret) + return ret; + + sr_cr[1] =3D cr; + + ret =3D spi_nor_write_sr(nor, sr_cr, 2); + if (ret) + return ret; + + sr_written =3D sr_cr[0]; + + ret =3D spi_nor_read_sr(nor, &sr_cr[0]); + if (ret) + return ret; + + if (sr_written !=3D sr_cr[0]) { + dev_err(nor->dev, "SR1: Read back test failed\n"); + return -EIO; + } + + if (nor->flags & SNOR_F_NO_READ_CR) + return 0; + + ret =3D spi_nor_read_cr(nor, &sr_cr[1]); + if (ret) + return ret; + + if (cr !=3D sr_cr[1]) { + dev_err(nor->dev, "CR: read back test failed\n"); + return -EIO; + } + + return 0; +} + +/** * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure t= hat * the byte written match the received value without affecting other bits = in the * Status Register 1 and 2. @@ -2051,111 +2104,29 @@ static int macronix_quad_enable(struct spi_nor *no= r) } =20 /** - * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Registe= r. - * @nor: pointer to a 'struct spi_nor' + * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Stat= us + * Register 2. + * @nor: pointer to a 'struct spi_nor'. * - * Set the Quad Enable (QE) bit in the Configuration Register. - * This function should be used with QSPI memories not supporting the Read - * Configuration Register (35h) instruction. - * - * bit 1 of the Configuration Register is the QE bit for Spansion like QSP= I - * memories. + * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI mem= ories. * * Return: 0 on success, -errno otherwise. */ -static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) +static int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) { - u8 *sr_cr =3D nor->bouncebuf; int ret; - u8 sr_written; - - /* Keep the current value of the Status Register. */ - ret =3D spi_nor_read_sr(nor, &sr_cr[0]); - if (ret) - return ret; - - sr_cr[1] =3D SR2_QUAD_EN_BIT1; - - ret =3D spi_nor_write_sr(nor, sr_cr, 2); - if (ret) - return ret; =20 - sr_written =3D sr_cr[0]; - - ret =3D spi_nor_read_sr(nor, &sr_cr[0]); - if (ret) - return ret; - - if (sr_cr[0] !=3D sr_written) { - dev_err(nor->dev, "SR1: Read back test failed\n"); - return -EIO; - } - - return 0; -} - -/** - * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. - * @nor: pointer to a 'struct spi_nor' - * - * Set the Quad Enable (QE) bit in the Configuration Register. - * This function should be used with QSPI memories supporting the Read - * Configuration Register (35h) instruction. - * - * bit 1 of the Configuration Register is the QE bit for Spansion like QSP= I - * memories. - * - * Return: 0 on success, -errno otherwise. - */ -static int spansion_read_cr_quad_enable(struct spi_nor *nor) -{ - u8 *sr_cr =3D nor->bouncebuf; - int ret; - u8 sr_written; + if (nor->flags & SNOR_F_NO_READ_CR) + return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1); =20 - /* Check current Quad Enable bit value. */ - ret =3D spi_nor_read_cr(nor, &sr_cr[1]); + ret =3D spi_nor_read_cr(nor, &nor->bouncebuf[0]); if (ret) return ret; =20 - if (sr_cr[1] & SR2_QUAD_EN_BIT1) + if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) return 0; =20 - sr_cr[1] |=3D SR2_QUAD_EN_BIT1; - - /* Keep the current value of the Status Register. */ - ret =3D spi_nor_read_sr(nor, &sr_cr[0]); - if (ret) - return ret; - - ret =3D spi_nor_write_sr(nor, sr_cr, 2); - if (ret) - return ret; - - sr_written =3D sr_cr[0]; - - ret =3D spi_nor_read_sr(nor, &sr_cr[0]); - if (ret) - return ret; - - if (sr_written !=3D sr_cr[0]) { - dev_err(nor->dev, "SR1: Read back test failed\n"); - return -EIO; - } - - sr_written =3D sr_cr[1]; - - /* Read back and check it. */ - ret =3D spi_nor_read_cr(nor, &sr_cr[1]); - if (ret) - return ret; - - if (sr_cr[1] !=3D sr_written) { - dev_err(nor->dev, "SR2: Read back test failed\n"); - return -EIO; - } - - return 0; + return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); } =20 /** @@ -2235,7 +2206,7 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) * * Read-modify-write function that clears the Block Protection bits from t= he * Status Register without affecting other bits. The function is tightly - * coupled with the spansion_read_cr_quad_enable() function. Both assume t= hat + * coupled with the spi_nor_sr2_bit1_quad_enable() function. Both assume t= hat * the Write Register with 16 bits, together with the Read Configuration * Register (35h) instructions are supported. * @@ -3753,7 +3724,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, * supported. */ nor->flags |=3D SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR; - params->quad_enable =3D spansion_no_read_cr_quad_enable; + params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; break; =20 case BFPT_DWORD15_QER_SR1_BIT6: @@ -3775,7 +3746,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, */ nor->flags |=3D SNOR_F_HAS_16BIT_SR; =20 - params->quad_enable =3D spansion_read_cr_quad_enable; + params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; break; =20 default: @@ -4738,7 +4709,7 @@ static void spi_nor_info_init_params(struct spi_nor *= nor) u8 i, erase_mask; =20 /* Initialize legacy flash parameters and settings. */ - params->quad_enable =3D spansion_read_cr_quad_enable; + params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; params->set_4byte =3D spansion_set_4byte; params->setup =3D spi_nor_default_setup; /* Default to 16-bit Write Status (01h) Command */ @@ -4955,7 +4926,7 @@ static int spi_nor_init(struct spi_nor *nor) int err; =20 if (nor->clear_sr_bp) { - if (nor->params.quad_enable =3D=3D spansion_read_cr_quad_enable) + if (nor->params.quad_enable =3D=3D spi_nor_sr2_bit1_quad_enable) nor->clear_sr_bp =3D spi_nor_spansion_clear_sr_bp; =20 err =3D nor->clear_sr_bp(nor); --=20 2.9.5