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From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>,
	<linux-pm@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s)
Date: Fri, 1 Nov 2019 14:33:59 +0200	[thread overview]
Message-ID: <20191101123359.GG27141@pdeschrijver-desktop.Nvidia.com> (raw)
In-Reply-To: <40de641f-c38e-51ee-ae27-c5db468c45b5@gmail.com>

On Tue, Oct 29, 2019 at 03:47:56AM +0300, Dmitry Osipenko wrote:
..

> >>>> It would be useful to switch the power state terminology to the one used
> >>>> for later chips:
> >>>>
> >>>> LP0 becomes SC7
> >>>> LP1 becomes C1
> >>>> LP2 becomes CC7
> >>>>
> >>>> Meaning of these states is as follows
> >>>>
> >>>> C is a core state:
> >>>>
> >>>> C1 clock gating
> >>>> C2 not defined
> >>>> C3 not defined
> >>>> C4 not defined
> >>>> C5 not defined
> >>>> C6 not defined for ARM cores
> >>>> C7 power-gating
> >>>>
> >>>> CC is a CPU cluster C state:
> >>>>
> >>>> CC1 cluster clock gated
> >>>> CC2 not defined
> >>>> CC3 fmax@Vmin: not used prior to Tegra186
> >>>> CC4: cluster retention: no longer supported
> >>>> CC5: not defined
> >>>> CC6: cluster power gating
> >>>> CC7: cluster rail gating
> >>>>
> >>>> SC is a System C state:
> >>>>
> >>>> SC1: not defined
> >>>> SC2: not defined
> >>>> SC3: not defined
> >>>> SC4: not defined
> >>>> SC5: not defined
> >>>> SC6: not defined
> >>>> SC7: VDD_SOC off
> >>>
> >>> Hello Peter,
> >>>
> >>> But new "drivers/cpuidle/cpuidle-tegra.c" uses exactly that terminology,
> >>> please see "cpuidle: Refactor and move NVIDIA Tegra20 driver into
> >>> drivers/cpuidle/" and further patches. Am I missing something? Or do you
> >>> want the renaming to be a separate patch?
> >>>
> >>
> >> Or maybe you're suggesting to change the names everywhere and not only
> >> in the cpuidle driver? Please clarify :)
> > 
> > At least some of the variable and function names still say lp2?
> 
> The cpuidle driver uses LP2 terminology for everything that comes from
> the external arch / firmware includes. But it says CC6 for everything
> that is internal to the driver. So yes, there is a bit of new/old
> terminology mixing in the code.
> 
> The arch code / PMC driver / TF firmware are all saying LP2. The LP2
> naming is also a part of the device-tree binding.
> 
> It will be a lot of mess to rename the mach-tegra/pm.c code. I guess
> eventually it could be moved to drivers/soc/, so maybe it will be better
> to postpone the renaming until then?

Or maybe add a comment somewhere indicating:

LP2 = CC6
LP1 = C1
LP0 = SC7

TF predates the new naming, so that may make some sense.

Peter.

  reply	other threads:[~2019-11-01 12:34 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-15 16:59 Dmitry Osipenko
2019-10-15 16:59 ` [PATCH v6 01/18] ARM: tegra: Compile sleep-tegra20/30.S unconditionally Dmitry Osipenko
2019-10-15 16:59 ` [PATCH v6 02/18] ARM: tegra: Add tegra_pm_park_secondary_cpu() Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 03/18] ARM: tegra: Remove pen-locking from cpuidle-tegra20 Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 04/18] ARM: tegra: Change tegra_set_cpu_in_lp2() type to void Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 05/18] ARM: tegra: Propagate error from tegra_idle_lp2_last() Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 06/18] ARM: tegra: Expose PM functions required for new cpuidle driver Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 07/18] ARM: tegra: Rename some of the newly exposed PM functions Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 08/18] ARM: tegra: Make outer_disable() open-coded Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 09/18] clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP Dmitry Osipenko
2019-10-29 13:19   ` Thierry Reding
2019-10-15 17:00 ` [PATCH v6 10/18] arm: tegra20: cpuidle: Handle case where secondary CPU hangs on entering LP2 Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 11/18] arm: tegra20: cpuidle: Make abort_flag atomic Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 12/18] arm: tegra20/30: cpuidle: Remove unnecessary memory barrier Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 13/18] cpuidle: Refactor and move NVIDIA Tegra20 driver into drivers/cpuidle/ Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 14/18] cpuidle: tegra: Squash Tegra30 driver into the common driver Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 15/18] cpuidle: tegra: Support CPU cluster power-down state on Tegra30 Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 16/18] cpuidle: tegra: Squash Tegra114 driver into the common driver Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 17/18] ARM: multi_v7_defconfig: Enable Tegra cpuidle driver Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 18/18] ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig Dmitry Osipenko
2019-10-16 19:21 ` [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Peter De Schrijver
2019-10-16 19:47   ` Dmitry Osipenko
2019-10-16 20:14     ` Dmitry Osipenko
2019-10-28 14:04       ` Peter De Schrijver
2019-10-29  0:47         ` Dmitry Osipenko
2019-11-01 12:33           ` Peter De Schrijver [this message]
2019-11-01 13:22             ` Dmitry Osipenko
2019-11-01 21:30               ` Dmitry Osipenko

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