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Sat, 2 Nov 2019 11:23:52 +0000 From: To: , CC: , , , , Subject: [PATCH v4 16/20] mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 Thread-Topic: [PATCH v4 16/20] mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 Thread-Index: AQHVkXABFg3WNTfgP0OsvbRpAkLphw== Date: Sat, 2 Nov 2019 11:23:52 +0000 Message-ID: <20191102112316.20715-17-tudor.ambarus@microchip.com> References: <20191102112316.20715-1-tudor.ambarus@microchip.com> In-Reply-To: <20191102112316.20715-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR07CA0143.eurprd07.prod.outlook.com (2603:10a6:802:16::30) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [86.120.239.29] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3581e708-ac1f-48f1-d792-08d75f872409 x-ms-traffictypediagnostic: MN2PR11MB3711: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 3581e708-ac1f-48f1-d792-08d75f872409 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Nov 2019 11:23:52.8571 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: KUPYw74cVIP/MWodCuy3XTGQCDgzTN3eHv5FbGyBkSQJi6AMRDkply9EGRHzsaspOyq+IHjzMtRi3ax2oIr8U+ucMVSruODBd6r344I2Tks= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3711 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20, refers to this bit as "bit 1 of the status register 2". Rename the macro accordingly. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 10 +++++----- include/linux/mtd/spi-nor.h | 4 +--- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 8f11c00e8ae5..e367a4862ec1 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1026,7 +1026,7 @@ static int spi_nor_write_16bit_sr_and_check(struct sp= i_nor *nor, u8 sr1) * Write Status (01h) command is available just for the cases * in which the QE bit is described in SR2 at BIT(1). */ - sr_cr[1] =3D CR_QUAD_EN_SPAN; + sr_cr[1] =3D SR2_QUAD_EN_BIT1; } else { sr_cr[1] =3D 0; } @@ -2074,7 +2074,7 @@ static int spansion_no_read_cr_quad_enable(struct spi= _nor *nor) if (ret) return ret; =20 - sr_cr[1] =3D CR_QUAD_EN_SPAN; + sr_cr[1] =3D SR2_QUAD_EN_BIT1; =20 ret =3D spi_nor_write_sr(nor, sr_cr, 2); if (ret) @@ -2118,10 +2118,10 @@ static int spansion_read_cr_quad_enable(struct spi_= nor *nor) if (ret) return ret; =20 - if (sr_cr[1] & CR_QUAD_EN_SPAN) + if (sr_cr[1] & SR2_QUAD_EN_BIT1) return 0; =20 - sr_cr[1] |=3D CR_QUAD_EN_SPAN; + sr_cr[1] |=3D SR2_QUAD_EN_BIT1; =20 /* Keep the current value of the Status Register. */ ret =3D spi_nor_read_sr(nor, sr_cr); @@ -2256,7 +2256,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_no= r *nor) * When the configuration register Quad Enable bit is one, only the * Write Status (01h) command with two data bytes may be used. */ - if (sr_cr[1] & CR_QUAD_EN_SPAN) { + if (sr_cr[1] & SR2_QUAD_EN_BIT1) { ret =3D spi_nor_read_sr(nor, sr_cr); if (ret) return ret; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d6ec55cc6d97..f626e0e52909 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -144,10 +144,8 @@ #define FSR_P_ERR BIT(4) /* Program operation status */ #define FSR_PT_ERR BIT(1) /* Protection error bit */ =20 -/* Configuration Register bits. */ -#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ - /* Status Register 2 bits. */ +#define SR2_QUAD_EN_BIT1 BIT(1) #define SR2_QUAD_EN_BIT7 BIT(7) =20 /* Supported SPI protocols */ --=20 2.9.5