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Sat, 2 Nov 2019 11:23:56 +0000 From: To: , CC: , , , , Subject: [PATCH v4 18/20] mtd: spi-nor: Rename macronix_quad_enable to spi_nor_sr1_bit6_quad_enable Thread-Topic: [PATCH v4 18/20] mtd: spi-nor: Rename macronix_quad_enable to spi_nor_sr1_bit6_quad_enable Thread-Index: AQHVkXADY6j1zfPLZU+XlaRtPvq+6A== Date: Sat, 2 Nov 2019 11:23:56 +0000 Message-ID: <20191102112316.20715-19-tudor.ambarus@microchip.com> References: <20191102112316.20715-1-tudor.ambarus@microchip.com> In-Reply-To: <20191102112316.20715-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR07CA0143.eurprd07.prod.outlook.com (2603:10a6:802:16::30) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [86.120.239.29] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f59bb2b8-a19e-4d6d-b50a-08d75f87262c x-ms-traffictypediagnostic: MN2PR11MB3711: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7219; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: f59bb2b8-a19e-4d6d-b50a-08d75f87262c X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Nov 2019 11:23:56.4770 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 2Kw8DSlM0F71xJTab8Gegy9CqglxQv6DVZTYFH+K1FerutHWsuQ5VqGRLKLAo2Spnykr+3JkVf/pVkGraqCVikTE4LocZgxj/+ArTWnNJ+o= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3711 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Rename method to a generic name: spi_nor_sr1_bit6_quad_enable(). Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 19 +++++++++---------- include/linux/mtd/spi-nor.h | 2 +- 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 8bc29cc073a0..85e5a56fb2d7 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -2078,16 +2078,15 @@ static int spi_nor_is_locked(struct mtd_info *mtd, = loff_t ofs, uint64_t len) } =20 /** - * macronix_quad_enable() - set QE bit in Status Register. + * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Stat= us + * Register 1. * @nor: pointer to a 'struct spi_nor' * - * Set the Quad Enable (QE) bit in the Status Register. - * - * bit 6 of the Status Register is the QE bit for Macronix like QSPI memor= ies. + * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI mem= ories. * * Return: 0 on success, -errno otherwise. */ -static int macronix_quad_enable(struct spi_nor *nor) +static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) { int ret; =20 @@ -2095,10 +2094,10 @@ static int macronix_quad_enable(struct spi_nor *nor= ) if (ret) return ret; =20 - if (nor->bouncebuf[0] & SR_QUAD_EN_MX) + if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) return 0; =20 - nor->bouncebuf[0] |=3D SR_QUAD_EN_MX; + nor->bouncebuf[0] |=3D SR1_QUAD_EN_BIT6; =20 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); } @@ -2349,7 +2348,7 @@ static void gd25q256_default_init(struct spi_nor *nor= ) * indicate the quad_enable method for this case, we need * to set it in the default_init fixup hook. */ - nor->params.quad_enable =3D macronix_quad_enable; + nor->params.quad_enable =3D spi_nor_sr1_bit6_quad_enable; } =20 static struct spi_nor_fixups gd25q256_fixups =3D { @@ -3729,7 +3728,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, =20 case BFPT_DWORD15_QER_SR1_BIT6: nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; - params->quad_enable =3D macronix_quad_enable; + params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; break; =20 case BFPT_DWORD15_QER_SR2_BIT7: @@ -4627,7 +4626,7 @@ static int spi_nor_setup(struct spi_nor *nor, =20 static void macronix_set_default_init(struct spi_nor *nor) { - nor->params.quad_enable =3D macronix_quad_enable; + nor->params.quad_enable =3D spi_nor_sr1_bit6_quad_enable; nor->params.set_4byte =3D macronix_set_4byte; } =20 diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index f626e0e52909..6d703df97f13 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -133,7 +133,7 @@ #define SR_E_ERR BIT(5) #define SR_P_ERR BIT(6) =20 -#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ +#define SR1_QUAD_EN_BIT6 BIT(6) =20 /* Enhanced Volatile Configuration Register bits */ #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ --=20 2.9.5