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Sat, 2 Nov 2019 11:23:27 +0000 From: To: , CC: , , , , Subject: [PATCH v4 02/20] mtd: spi-nor: Print debug info inside Reg Ops methods Thread-Topic: [PATCH v4 02/20] mtd: spi-nor: Print debug info inside Reg Ops methods Thread-Index: AQHVkW/yKhSneiiRq0eaAq+0GWESnA== Date: Sat, 2 Nov 2019 11:23:27 +0000 Message-ID: <20191102112316.20715-3-tudor.ambarus@microchip.com> References: <20191102112316.20715-1-tudor.ambarus@microchip.com> In-Reply-To: <20191102112316.20715-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR07CA0143.eurprd07.prod.outlook.com (2603:10a6:802:16::30) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [86.120.239.29] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3dae966d-8cb5-42ec-0ddd-08d75f8714a9 x-ms-traffictypediagnostic: MN2PR11MB3711: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1751; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 3dae966d-8cb5-42ec-0ddd-08d75f8714a9 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Nov 2019 11:23:27.1539 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: t5nFjzCfMiFKWTIEmjIJmNh12xR8ccWCkKB9tqZZ9XPi4f0JJFYRV+xr6qyE0o4wHMyIS1koqT9hEn1TqxSXMZU6//4wWliOYs14NwdWXMc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3711 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus Spare the callers of printing debug messages by themselves. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spi-nor.c | 169 +++++++++++++++++++++++++++++++-------= ---- 1 file changed, 127 insertions(+), 42 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index eca6bce7c336..0cb3122e74ad 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -394,6 +394,8 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, = loff_t to, size_t len, */ static int spi_nor_write_enable(struct spi_nor *nor) { + int ret; + if (nor->spimem) { struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1), @@ -401,10 +403,16 @@ static int spi_nor_write_enable(struct spi_nor *nor) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, + NULL, 0); } =20 - return nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, NULL, 0); + if (ret) + dev_dbg(nor->dev, "error %d on Write Enable\n", ret); + + return ret; } =20 /* @@ -412,6 +420,8 @@ static int spi_nor_write_enable(struct spi_nor *nor) */ static int spi_nor_write_disable(struct spi_nor *nor) { + int ret; + if (nor->spimem) { struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1), @@ -419,10 +429,16 @@ static int spi_nor_write_disable(struct spi_nor *nor) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, + NULL, 0); } =20 - return nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); + if (ret) + dev_dbg(nor->dev, "error %d on Write Disable\n", ret); + + return ret; } =20 /** @@ -524,6 +540,8 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) */ static int spi_nor_write_sr(struct spi_nor *nor, u8 val) { + int ret; + nor->bouncebuf[0] =3D val; if (nor->spimem) { struct spi_mem_op op =3D @@ -532,15 +550,23 @@ static int spi_nor_write_sr(struct spi_nor *nor, u8 v= al) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR, + nor->bouncebuf, 1); } =20 - return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR, - nor->bouncebuf, 1); + if (ret) + dev_dbg(nor->dev, "error %d writing SR\n", ret); + + return ret; + } =20 static int macronix_set_4byte(struct spi_nor *nor, bool enable) { + int ret; + if (nor->spimem) { struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? @@ -551,12 +577,18 @@ static int macronix_set_4byte(struct spi_nor *nor, bo= ol enable) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, + enable ? SPINOR_OP_EN4B : + SPINOR_OP_EX4B, + NULL, 0); } =20 - return nor->controller_ops->write_reg(nor, enable ? SPINOR_OP_EN4B : - SPINOR_OP_EX4B, - NULL, 0); + if (ret) + dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); + + return ret; } =20 static int st_micron_set_4byte(struct spi_nor *nor, bool enable) @@ -572,6 +604,8 @@ static int st_micron_set_4byte(struct spi_nor *nor, boo= l enable) =20 static int spansion_set_4byte(struct spi_nor *nor, bool enable) { + int ret; + nor->bouncebuf[0] =3D enable << 7; =20 if (nor->spimem) { @@ -581,15 +615,22 @@ static int spansion_set_4byte(struct spi_nor *nor, bo= ol enable) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR, + nor->bouncebuf, 1); } =20 - return nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR, - nor->bouncebuf, 1); + if (ret) + dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); + + return ret; } =20 static int spi_nor_write_ear(struct spi_nor *nor, u8 ear) { + int ret; + nor->bouncebuf[0] =3D ear; =20 if (nor->spimem) { @@ -599,11 +640,16 @@ static int spi_nor_write_ear(struct spi_nor *nor, u8 = ear) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR, + nor->bouncebuf, 1); } =20 - return nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR, - nor->bouncebuf, 1); + if (ret) + dev_dbg(nor->dev, "error %d writing EAR\n", ret); + + return ret; } =20 static int winbond_set_4byte(struct spi_nor *nor, bool enable) @@ -628,6 +674,8 @@ static int winbond_set_4byte(struct spi_nor *nor, bool = enable) =20 static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr) { + int ret; + if (nor->spimem) { struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1), @@ -635,10 +683,16 @@ static int spi_nor_xread_sr(struct spi_nor *nor, u8 *= sr) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_IN(1, sr, 1)); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, + sr, 1); } =20 - return nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, sr, 1); + if (ret) + dev_dbg(nor->dev, "error %d reading XRDSR\n", ret); + + return ret; } =20 static int s3an_sr_ready(struct spi_nor *nor) @@ -646,16 +700,16 @@ static int s3an_sr_ready(struct spi_nor *nor) int ret; =20 ret =3D spi_nor_xread_sr(nor, nor->bouncebuf); - if (ret) { - dev_dbg(nor->dev, "error %d reading XRDSR\n", ret); + if (ret) return ret; - } =20 return !!(nor->bouncebuf[0] & XSR_RDY); } =20 static int spi_nor_clear_sr(struct spi_nor *nor) { + int ret; + if (nor->spimem) { struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1), @@ -663,10 +717,16 @@ static int spi_nor_clear_sr(struct spi_nor *nor) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, + NULL, 0); } =20 - return nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, NULL, 0); + if (ret) + dev_dbg(nor->dev, "error %d clearing SR\n", ret); + + return ret; } =20 static int spi_nor_sr_ready(struct spi_nor *nor) @@ -692,6 +752,8 @@ static int spi_nor_sr_ready(struct spi_nor *nor) =20 static int spi_nor_clear_fsr(struct spi_nor *nor) { + int ret; + if (nor->spimem) { struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1), @@ -699,10 +761,16 @@ static int spi_nor_clear_fsr(struct spi_nor *nor) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, + NULL, 0); } =20 - return nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0); + if (ret) + dev_dbg(nor->dev, "error %d clearing FSR\n", ret); + + return ret; } =20 static int spi_nor_fsr_ready(struct spi_nor *nor) @@ -839,6 +907,8 @@ static int spi_nor_write_sr_and_check(struct spi_nor *n= or, u8 status_new, =20 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) { + int ret; + if (nor->spimem) { struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1), @@ -846,14 +916,22 @@ static int spi_nor_write_sr2(struct spi_nor *nor, con= st u8 *sr2) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_OUT(1, sr2, 1)); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, + sr2, 1); } =20 - return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1); + if (ret) + dev_dbg(nor->dev, "error %d writing SR2\n", ret); + + return ret; } =20 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) { + int ret; + if (nor->spimem) { struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1), @@ -861,10 +939,16 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *= sr2) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_IN(1, sr2, 1)); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, + sr2, 1); } =20 - return nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1); + if (ret) + dev_dbg(nor->dev, "error %d reading SR2\n", ret); + + return ret; } =20 /* @@ -874,6 +958,8 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr= 2) */ static int spi_nor_erase_chip(struct spi_nor *nor) { + int ret; + dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); =20 if (nor->spimem) { @@ -883,11 +969,16 @@ static int spi_nor_erase_chip(struct spi_nor *nor) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); =20 - return spi_mem_exec_op(nor->spimem, &op); + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE, + NULL, 0); } =20 - return nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE, - NULL, 0); + if (ret) + dev_dbg(nor->dev, "error %d erasing chip\n", ret); + + return ret; } =20 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) @@ -1934,10 +2025,8 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) spi_nor_write_enable(nor); =20 ret =3D spi_nor_write_sr2(nor, sr2); - if (ret) { - dev_dbg(nor->dev, "error while writing status register 2\n"); + if (ret) return ret; - } =20 ret =3D spi_nor_wait_till_ready(nor); if (ret) @@ -1977,10 +2066,8 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor) spi_nor_write_enable(nor); =20 ret =3D spi_nor_write_sr(nor, nor->bouncebuf[0] & ~mask); - if (ret) { - dev_dbg(nor->dev, "write to status register failed\n"); + if (ret) return ret; - } =20 return spi_nor_wait_till_ready(nor); } @@ -2739,10 +2826,8 @@ static int s3an_nor_setup(struct spi_nor *nor, int ret; =20 ret =3D spi_nor_xread_sr(nor, nor->bouncebuf); - if (ret) { - dev_dbg(nor->dev, "error %d reading XRDSR\n", ret); + if (ret) return ret; - } =20 nor->erase_opcode =3D SPINOR_OP_XSE; nor->program_opcode =3D SPINOR_OP_XPP; --=20 2.9.5