From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A74B0CA9ECF for ; Mon, 4 Nov 2019 13:25:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7C4F721D7D for ; Mon, 4 Nov 2019 13:25:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="TXm7YF9n" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729241AbfKDNZ6 (ORCPT ); Mon, 4 Nov 2019 08:25:58 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:16686 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727913AbfKDNZz (ORCPT ); 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Mon, 4 Nov 2019 14:25:37 +0100 (CET) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 542D92BFC79; Mon, 4 Nov 2019 14:25:37 +0100 (CET) Received: from SAFEX1HUBCAS21.st.com (10.75.90.45) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 4 Nov 2019 14:25:37 +0100 Received: from localhost (10.201.22.222) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 4 Nov 2019 14:25:36 +0100 From: Christophe Roullier To: , , , , , , CC: , , , , , , Subject: [PATCH net-next 1/4] net: ethernet: stmmac: Add support for syscfg clock Date: Mon, 4 Nov 2019 14:25:30 +0100 Message-ID: <20191104132533.5153-2-christophe.roullier@st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191104132533.5153-1-christophe.roullier@st.com> References: <20191104132533.5153-1-christophe.roullier@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.22.222] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-11-04_08:2019-11-04,2019-11-04 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add optional support for syscfg clock in dwmac-stm32.c Now Syscfg clock is activated automatically when syscfg registers are used Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 36 +++++++++++++------ 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 4ef041bdf6a1..7e6619868cc1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -152,23 +152,32 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare) int ret = 0; if (prepare) { - ret = clk_prepare_enable(dwmac->syscfg_clk); - if (ret) - return ret; - + if (dwmac->syscfg_clk) { + ret = clk_prepare_enable(dwmac->syscfg_clk); + if (ret) + return ret; + } if (dwmac->clk_eth_ck) { ret = clk_prepare_enable(dwmac->clk_eth_ck); if (ret) { - clk_disable_unprepare(dwmac->syscfg_clk); + if (dwmac->syscfg_clk) + goto unprepare_syscfg; return ret; } } } else { - clk_disable_unprepare(dwmac->syscfg_clk); + if (dwmac->syscfg_clk) + clk_disable_unprepare(dwmac->syscfg_clk); + if (dwmac->clk_eth_ck) clk_disable_unprepare(dwmac->clk_eth_ck); } return ret; + +unprepare_syscfg: + clk_disable_unprepare(dwmac->syscfg_clk); + + return ret; } static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) @@ -296,7 +305,7 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, { struct platform_device *pdev = to_platform_device(dev); struct device_node *np = dev->of_node; - int err = 0; + int err; /* Gigabit Ethernet 125MHz clock selection. */ dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel"); @@ -320,13 +329,17 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, return PTR_ERR(dwmac->clk_ethstp); } - /* Clock for sysconfig */ + /* Optional Clock for sysconfig */ dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk"); if (IS_ERR(dwmac->syscfg_clk)) { - dev_err(dev, "No syscfg clock provided...\n"); - return PTR_ERR(dwmac->syscfg_clk); + err = PTR_ERR(dwmac->syscfg_clk); + if (err != -ENOENT) + return err; + dwmac->syscfg_clk = NULL; } + err = 0; + /* Get IRQ information early to have an ability to ask for deferred * probe if needed before we went too far with resource allocation. */ @@ -436,7 +449,8 @@ static int stm32mp1_suspend(struct stm32_dwmac *dwmac) return ret; clk_disable_unprepare(dwmac->clk_tx); - clk_disable_unprepare(dwmac->syscfg_clk); + if (dwmac->syscfg_clk) + clk_disable_unprepare(dwmac->syscfg_clk); if (dwmac->clk_eth_ck) clk_disable_unprepare(dwmac->clk_eth_ck); -- 2.17.1