From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C47C8C5DF60 for ; Tue, 5 Nov 2019 20:04:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 88AAC217F5 for ; Tue, 5 Nov 2019 20:04:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728709AbfKEUE5 (ORCPT ); Tue, 5 Nov 2019 15:04:57 -0500 Received: from foss.arm.com ([217.140.110.172]:58682 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726208AbfKEUE5 (ORCPT ); Tue, 5 Nov 2019 15:04:57 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 47F387AD; Tue, 5 Nov 2019 12:04:56 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C3D0B3FBD2; Tue, 5 Nov 2019 01:27:03 -0800 (PST) Date: Tue, 5 Nov 2019 09:27:01 +0000 From: Mark Rutland To: Bhupesh Sharma Cc: linux-arm-kernel@lists.infradead.org, bhupesh.linux@gmail.com, James Morse , Will Deacon , Steve Capper , Catalin Marinas , Ard Biesheuvel , linux-kernel@vger.kernel.org, kexec@lists.infradead.org Subject: Re: [PATCH] arm64: mm: Remove MAX_USER_VA_BITS definition Message-ID: <20191105092701.GD4743@lakrids.cambridge.arm.com> References: <1572904606-27961-1-git-send-email-bhsharma@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1572904606-27961-1-git-send-email-bhsharma@redhat.com> User-Agent: Mutt/1.11.1+11 (2f07cb52) (2018-12-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 05, 2019 at 03:26:46AM +0530, Bhupesh Sharma wrote: > commit 9b31cf493ffa ("arm64: mm: Introduce MAX_USER_VA_BITS definition") > introduced the MAX_USER_VA_BITS definition, which was used to support > the arm64 mm use-cases where the user-space could use 52-bit virtual > addresses whereas the kernel-space would still could a maximum of 48-bit > virtual addressing. > > But, now with commit b6d00d47e81a ("arm64: mm: Introduce 52-bit Kernel > VAs"), we removed the 52-bit user/48-bit kernel kconfig option and hence > there is no longer any scenario where user VA != kernel VA size > (even with CONFIG_ARM64_FORCE_52BIT enabled, the same is true). > > Hence we can do away with the MAX_USER_VA_BITS macro as it is equal to > VA_BITS (maximum VA space size) in all possible use-cases. Note that > even though the 'vabits_actual' value would be 48 for arm64 hardware > which don't support LVA-8.2 extension (even when CONFIG_ARM64_VA_BITS_52 > is enabled), VA_BITS would still be set to a value 52. Hence this change > would be safe in all possible VA address space combinations. > > Cc: James Morse > Cc: Mark Rutland > Cc: Will Deacon > Cc: Steve Capper > Cc: Catalin Marinas > Cc: Ard Biesheuvel > Cc: linux-kernel@vger.kernel.org > Cc: kexec@lists.infradead.org > Signed-off-by: Bhupesh Sharma As the commit message says, there should be no functional change as a result of this patch, and it looks like a nice cleanup to me: Reviewed-by: Mark Rutland Mark. > --- > arch/arm64/include/asm/memory.h | 6 ------ > arch/arm64/include/asm/pgtable-hwdef.h | 2 +- > arch/arm64/include/asm/processor.h | 2 +- > 3 files changed, 2 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h > index c23c47360664..a4f9ca5479b0 100644 > --- a/arch/arm64/include/asm/memory.h > +++ b/arch/arm64/include/asm/memory.h > @@ -69,12 +69,6 @@ > #define KERNEL_START _text > #define KERNEL_END _end > > -#ifdef CONFIG_ARM64_VA_BITS_52 > -#define MAX_USER_VA_BITS 52 > -#else > -#define MAX_USER_VA_BITS VA_BITS > -#endif > - > /* > * Generic and tag-based KASAN require 1/8th and 1/16th of the kernel virtual > * address space for the shadow region respectively. They can bloat the stack > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h > index 3df60f97da1f..d9fbd433cc17 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -69,7 +69,7 @@ > #define PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS) > #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) > #define PGDIR_MASK (~(PGDIR_SIZE-1)) > -#define PTRS_PER_PGD (1 << (MAX_USER_VA_BITS - PGDIR_SHIFT)) > +#define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) > > /* > * Section address mask and size definitions. > diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h > index 5623685c7d13..586fcd4b1965 100644 > --- a/arch/arm64/include/asm/processor.h > +++ b/arch/arm64/include/asm/processor.h > @@ -9,7 +9,7 @@ > #define __ASM_PROCESSOR_H > > #define KERNEL_DS UL(-1) > -#define USER_DS ((UL(1) << MAX_USER_VA_BITS) - 1) > +#define USER_DS ((UL(1) << VA_BITS) - 1) > > /* > * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is > -- > 2.7.4 >