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Thu, 7 Nov 2019 08:42:01 +0000 From: To: , CC: , , , , Subject: [PATCH v5 4/6] mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 Thread-Topic: [PATCH v5 4/6] mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 Thread-Index: AQHVlUc52k8BvaRMI0OSG2EtSt3f5Q== Date: Thu, 7 Nov 2019 08:42:01 +0000 Message-ID: <20191107084135.22122-5-tudor.ambarus@microchip.com> References: <20191107084135.22122-1-tudor.ambarus@microchip.com> In-Reply-To: <20191107084135.22122-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM0PR10CA0060.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:150::40) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [109.166.128.4] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 7cb39618-276f-44f6-bca3-08d7635e5b6f x-ms-traffictypediagnostic: MN2PR11MB3824: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 7cb39618-276f-44f6-bca3-08d7635e5b6f X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Nov 2019 08:42:01.4755 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 5f2ezRStwHy/f2jkA+qKa8tWPpv0lgmN+FNnNkAt2hfvdjHvv2vzs9Z4u4QsAB0p2dWgrY7elTqeQ0EwY98XHBTYAguKOJf6fztuT/Y0l5o= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3824 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tudor Ambarus JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20, refers to this bit as "bit 1 of the status register 2". Rename the macro accordingly. Signed-off-by: Tudor Ambarus Reviewed-by: Vignesh Raghavendra --- drivers/mtd/spi-nor/spi-nor.c | 8 ++++---- include/linux/mtd/spi-nor.h | 4 +--- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index d33ad56d3b67..8c59b5220e2a 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1026,7 +1026,7 @@ static int spi_nor_write_16bit_sr_and_check(struct sp= i_nor *nor, u8 sr1) * Write Status (01h) command is available just for the cases * in which the QE bit is described in SR2 at BIT(1). */ - sr_cr[1] =3D CR_QUAD_EN_SPAN; + sr_cr[1] =3D SR2_QUAD_EN_BIT1; } else { sr_cr[1] =3D 0; } @@ -2074,7 +2074,7 @@ static int spansion_no_read_cr_quad_enable(struct spi= _nor *nor) if (ret) return ret; =20 - sr_cr[1] =3D CR_QUAD_EN_SPAN; + sr_cr[1] =3D SR2_QUAD_EN_BIT1; =20 ret =3D spi_nor_write_sr(nor, sr_cr, 2); if (ret) @@ -2118,10 +2118,10 @@ static int spansion_read_cr_quad_enable(struct spi_= nor *nor) if (ret) return ret; =20 - if (sr_cr[1] & CR_QUAD_EN_SPAN) + if (sr_cr[1] & SR2_QUAD_EN_BIT1) return 0; =20 - sr_cr[1] |=3D CR_QUAD_EN_SPAN; + sr_cr[1] |=3D SR2_QUAD_EN_BIT1; =20 /* Keep the current value of the Status Register. */ ret =3D spi_nor_read_sr(nor, sr_cr); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 11daecc5a83d..364309845de0 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -144,10 +144,8 @@ #define FSR_P_ERR BIT(4) /* Program operation status */ #define FSR_PT_ERR BIT(1) /* Protection error bit */ =20 -/* Configuration Register bits. */ -#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ - /* Status Register 2 bits. */ +#define SR2_QUAD_EN_BIT1 BIT(1) #define SR2_QUAD_EN_BIT7 BIT(7) =20 /* Supported SPI protocols */ --=20 2.9.5