On Mon 2019-11-11 19:29:22, Greg Kroah-Hartman wrote:
> From: Jean-Baptiste Maneyrol <JManeyrol@invensense.com>
> 
> [ Upstream commit 6e82ae6b8d11b948b74e71396efd8e074c415f44 ]
> 
> Some chips have a fifo overflow bit issue where the bit is always
> set. The result is that every data is dropped.
> 
> Change fifo overflow management by checking fifo count against
> a maximum value.
> 
> Add fifo size in chip hardware set of values.

> @@ -216,6 +213,18 @@ irqreturn_t inv_mpu6050_read_fifo(int irq, void *p)
>  	if (result)
>  		goto end_session;
>  	fifo_count = get_unaligned_be16(&data[0]);
> +
> +	/*
> +	 * Handle fifo overflow by resetting fifo.
> +	 * Reset if there is only 3 data set free remaining to mitigate
> +	 * possible delay between reading fifo count and fifo data.
> +	 */
> +	nb = 3 * bytes_per_datum;
> +	if (fifo_count >= st->hw->fifo_size - nb) {
> +		dev_warn(regmap_get_device(st->map), "fifo overflow reset\n");
> +		goto flush_fifo;
> +	}
> +
>  	/* compute and process all complete datum */
>  	nb = fifo_count / bytes_per_datum;
>  	inv_mpu6050_update_period(st, pf->timestamp, nb);

Would this make sense to reduce code duplication?

Signed-off-by: Pavel Machek <pavel@denx.de>

Best regards,
									Pavel

diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c
index 548e042f7b5b..9b9d90f41610 100644
--- a/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c
+++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c
@@ -232,16 +232,12 @@ irqreturn_t inv_mpu6050_read_fifo(int irq, void *p)
 		timestamp = inv_mpu6050_get_timestamp(st);
 		iio_push_to_buffers_with_timestamp(indio_dev, data, timestamp);
 	}
-
-end_session:
-	mutex_unlock(&st->lock);
-	iio_trigger_notify_done(indio_dev->trig);
-
-	return IRQ_HANDLED;
+	goto end_session;
 
 flush_fifo:
 	/* Flush HW and SW FIFOs. */
 	inv_reset_fifo(indio_dev);
+end_session:
 	mutex_unlock(&st->lock);
 	iio_trigger_notify_done(indio_dev->trig);
 

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