From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ECBDC432C3 for ; Tue, 19 Nov 2019 11:17:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7D2C9222F2 for ; Tue, 19 Nov 2019 11:17:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727802AbfKSLRj (ORCPT ); Tue, 19 Nov 2019 06:17:39 -0500 Received: from foss.arm.com ([217.140.110.172]:50930 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727296AbfKSLRj (ORCPT ); Tue, 19 Nov 2019 06:17:39 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 61DDAC86; Tue, 19 Nov 2019 03:17:38 -0800 (PST) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9772B3F703; Tue, 19 Nov 2019 03:17:37 -0800 (PST) Date: Tue, 19 Nov 2019 11:17:35 +0000 From: Andrew Murray To: Nicolas Saenz Julienne Cc: maz@kernel.org, linux-kernel@vger.kernel.org, Eric Anholt , Stefan Wahren , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Bjorn Helgaas , james.quinlan@broadcom.com, mbrugger@suse.com, phil@raspberrypi.org, jeremy.linton@arm.com, Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 2/6] dt-bindings: PCI: Add bindings for brcmstb's PCIe device Message-ID: <20191119111735.GQ43905@e119886-lin.cambridge.arm.com> References: <20191112155926.16476-1-nsaenzjulienne@suse.de> <20191112155926.16476-3-nsaenzjulienne@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191112155926.16476-3-nsaenzjulienne@suse.de> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 12, 2019 at 04:59:21PM +0100, Nicolas Saenz Julienne wrote: > From: Jim Quinlan > > The DT bindings description of the brcmstb PCIe device is described. > This node can only be used for now on the Raspberry Pi 4. > > Signed-off-by: Jim Quinlan > Co-developed-by: Nicolas Saenz Julienne > Signed-off-by: Nicolas Saenz Julienne > > --- > > Changes since v1: > - Fix commit Subject > - Remove linux,pci-domain > > This was based on Jim's original submission[1], converted to yaml and > adapted to the RPi4 case. > > [1] https://patchwork.kernel.org/patch/10605937/ > > .../bindings/pci/brcm,stb-pcie.yaml | 110 ++++++++++++++++++ > 1 file changed, 110 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > new file mode 100644 > index 000000000000..4cbb18821300 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > @@ -0,0 +1,110 @@ > +# SPDX-License-Identifier: GPL-2.0 I think in the last revision Rob asked you to change the license to the following: # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) Thanks, Andrew Murray > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Brcmstb PCIe Host Controller Device Tree Bindings > + > +maintainers: > + - Nicolas Saenz Julienne > + > +properties: > + compatible: > + const: brcm,bcm2711-pcie # The Raspberry Pi 4 > + > + reg: > + maxItems: 1 > + > + interrupts: > + minItems: 1 > + maxItems: 2 > + items: > + - description: PCIe host controller > + - description: builtin MSI controller > + > + interrupt-names: > + minItems: 1 > + maxItems: 2 > + items: > + - const: pcie > + - const: msi > + > + "#address-cells": > + const: 3 > + > + "#size-cells": > + const: 2 > + > + "#interrupt-cells": > + const: 1 > + > + interrupt-map-mask: true > + > + interrupt-map: true > + > + ranges: true > + > + dma-ranges: true > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: sw_pcie > + > + msi-controller: > + description: Identifies the node as an MSI controller. > + type: boolean > + > + msi-parent: > + description: MSI controller the device is capable of using. > + $ref: /schemas/types.yaml#/definitions/phandle > + > + brcm,enable-ssc: > + description: Indicates usage of spread-spectrum clocking. > + type: boolean > + > +required: > + - compatible > + - reg > + - "#address-cells" > + - "#size-cells" > + - "#interrupt-cells" > + - interrupt-map-mask > + - interrupt-map > + - ranges > + - dma-ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + scb { > + #address-cells = <2>; > + #size-cells = <1>; > + pcie0: pcie@7d500000 { > + compatible = "brcm,bcm2711-pcie"; > + reg = <0x0 0x7d500000 0x9310>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupts = , > + ; > + interrupt-names = "pcie", "msi"; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; > + msi-parent = <&pcie0>; > + msi-controller; > + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; > + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; > + brcm,enable-ssc; > + }; > + }; > -- > 2.24.0 >