From: "Daniel W. S. Almeida" <dwlsalmeida@gmail.com>
To: linus.walleij@linaro.org, corbet@lwn.net, bgolaszewski@baylibre.com
Cc: "Daniel W. S. Almeida" <dwlsalmeida@gmail.com>,
linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, skhan@linuxfoundation.org,
linux-kernel-mentees@lists.linuxfoundation.org
Subject: [PATCH] Documentation: gpio: driver.rst: Fix warnings
Date: Fri, 22 Nov 2019 00:47:02 -0300 [thread overview]
Message-ID: <20191122034702.58563-1-dwlsalmeida@gmail.com> (raw)
From: "Daniel W. S. Almeida" <dwlsalmeida@gmail.com>
Fix warnings due to incorrect rst markup. Also improved the presentation
a little without changing the underlying content.
Signed-off-by: Daniel W. S. Almeida <dwlsalmeida@gmail.com>
---
Documentation/driver-api/gpio/driver.rst | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/Documentation/driver-api/gpio/driver.rst b/Documentation/driver-api/gpio/driver.rst
index 3fdb32422f8a..c58f54783237 100644
--- a/Documentation/driver-api/gpio/driver.rst
+++ b/Documentation/driver-api/gpio/driver.rst
@@ -5,7 +5,7 @@ GPIO Driver Interface
This document serves as a guide for writers of GPIO chip drivers.
Each GPIO controller driver needs to include the following header, which defines
-the structures used to define a GPIO driver:
+the structures used to define a GPIO driver::
#include <linux/gpio/driver.h>
@@ -398,12 +398,15 @@ provided. A big portion of overhead code will be managed by gpiolib,
under the assumption that your interrupts are 1-to-1-mapped to the
GPIO line index:
- GPIO line offset Hardware IRQ
- 0 0
- 1 1
- 2 2
- ... ...
- ngpio-1 ngpio-1
+.. csv-table::
+ :header: GPIO line offset, Hardware IRQ
+
+ 0,0
+ 1,1
+ 2,2
+ ...,...
+ ngpio-1, ngpio-1
+
If some GPIO lines do not have corresponding IRQs, the bitmask valid_mask
and the flag need_valid_mask in gpio_irq_chip can be used to mask off some
@@ -413,7 +416,7 @@ The preferred way to set up the helpers is to fill in the
struct gpio_irq_chip inside struct gpio_chip before adding the gpio_chip.
If you do this, the additional irq_chip will be set up by gpiolib at the
same time as setting up the rest of the GPIO functionality. The following
-is a typical example of a cascaded interrupt handler using gpio_irq_chip:
+is a typical example of a cascaded interrupt handler using gpio_irq_chip::
/* Typical state container with dynamic irqchip */
struct my_gpio {
@@ -448,7 +451,7 @@ is a typical example of a cascaded interrupt handler using gpio_irq_chip:
return devm_gpiochip_add_data(dev, &g->gc, g);
The helper support using hierarchical interrupt controllers as well.
-In this case the typical set-up will look like this:
+In this case the typical set-up will look like this::
/* Typical state container with dynamic irqchip */
struct my_gpio {
--
2.24.0
next reply other threads:[~2019-11-22 3:55 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-22 3:47 Daniel W. S. Almeida [this message]
2019-11-22 12:59 ` Linus Walleij
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