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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: ghHhy7Cj4vBqx+a7MdEMTEj27GDhFPxXfGMwsdewFYHScoGi98mgXgUonyi0G2U4FufOa5+2AhMZpJEFymmA8Od0bMFNO+dZ1OoEDJgWXepZe5d2PNHcEpa7arlNIXuuhAxw+b/dcMTKiniM9MJHQNsLHLflJHuIZmhQoQDlVdt1L/YJun6/Rm/2tFGqdnULMVJ8T+U5s8bLGy3QoHfo6aePkdx88z72dfHqqvMo8fkGWpCwB11sv35lN9JRQwb8Nxa8a56XqapJ44Wxbzx2Ee8lzfKevte5DqLMnwd5dGYFaltec4bXPK6tKOIE1s7meLAWrF7Bc2RjaiVkioWsaZ9wk5BgOo1NXLkrcFEunDLT7EQTBzHaXhyDRBXVFtFqWlyOwN94YuVdZ6IYkjw5KalWfNoaI6Y3Hjg9Mx4WFaKkdFjD5hwk18DX3qdfEnYzmQFEE7NUb3rIMsvpZurI1u4AYjy/Xyfn/D50vx/Do4Y= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4bfd079e-f500-4a57-bd95-08d771a909a9 X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Nov 2019 13:11:52.4153 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: VTmTLjzMZFQLchCyxJG/DRkdYQt9ejqvQ6YnLKN4JVGVKlE6Pb+NE9cicre7SL3QoitAex1HKeZYxKEG5QRW+A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6752 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the device tree to support Google Coral Edge TPU, historicaly named as fsl-imx8mq-phanbell, a computer on module which can be used for AI/ML propose. It introduces a minimal enablement support for this module and was based on the i.MX 8MQ Phanbell Google Source Code for Coral=20 Edge TPU Mendel release: https://coral.googlesource.com/linux-imx/ Tested components: - PMIC; - USB-C OTG; - USB-C PWR; - micro-USB; - USB. Signed-off-by: Marco Franchi Reviewed-by: Fabio Estevam --- Changes since v2: - remove i.MX 8 MQ EVK from message log - fix memory size node arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mq-phanbell.dts | 405 ++++++++++++++++++ 2 files changed, 406 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 38e344a2f0ff..e50a934e2417 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-hummingboard-pulse.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-librem5-devkit.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-nitrogen.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-phanbell.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-pico-pi.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-zii-ultra-rmb3.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mq-zii-ultra-zest.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64= /boot/dts/freescale/imx8mq-phanbell.dts new file mode 100644 index 000000000000..08820ea72427 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8mq.dtsi" + +/ { + model =3D "Google i.MX8MQ Phanbell"; + compatible =3D "google,imx8mq-phanbell", "fsl,imx8mq"; + + chosen { + stdout-path =3D &uart1; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0x00000000 0x40000000 0 0x40000000>; + }; + + pmic_osc: clock-pmic { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "pmic_osc"; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "VSD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible =3D "regulator-gpio"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_dvfs>; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1000000>; + regulator-name =3D "gpio_dvfs"; + regulator-type =3D "voltage"; + gpios =3D <&gpio1 13 GPIO_ACTIVE_HIGH>; + states =3D <900000 0x1 1000000 0x0>; + }; +}; + +&A53_0 { + cpu-supply =3D <®_gpio_dvfs>; +}; + +&A53_1 { + cpu-supply =3D <®_gpio_dvfs>; +}; + +&A53_2 { + cpu-supply =3D <®_gpio_dvfs>; +}; + +&A53_3 { + cpu-supply =3D <®_gpio_dvfs>; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + status =3D "okay"; + + pmic: pmic@4b { + reg =3D <0x4b>; + compatible =3D "rohm,bd71837"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pmic>; + clocks =3D <&pmic_osc>; + clock-names =3D "osc"; + clock-output-names =3D "pmic_clk"; + interrupt-parent =3D <&gpio1>; + interrupts =3D <3 GPIO_ACTIVE_LOW>; + interrupt-names =3D "irq"; + + regulators { + buck1: BUCK1 { + regulator-name =3D "buck1"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1300000>; + regulator-boot-on; + regulator-ramp-delay =3D <1250>; + rohm,dvs-run-voltage =3D <900000>; + rohm,dvs-idle-voltage =3D <850000>; + rohm,dvs-suspend-voltage =3D <800000>; + }; + + buck2: BUCK2 { + regulator-name =3D "buck2"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1300000>; + regulator-boot-on; + regulator-ramp-delay =3D <1250>; + rohm,dvs-run-voltage =3D <1000000>; + rohm,dvs-idle-voltage =3D <900000>; + }; + + buck3: BUCK3 { + regulator-name =3D "buck3"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1300000>; + regulator-boot-on; + rohm,dvs-run-voltage =3D <1000000>; + }; + + buck4: BUCK4 { + regulator-name =3D "buck4"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1300000>; + regulator-boot-on; + rohm,dvs-run-voltage =3D <1000000>; + }; + + buck5: BUCK5 { + regulator-name =3D "buck5"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1350000>; + regulator-boot-on; + }; + + buck6: BUCK6 { + regulator-name =3D "buck6"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + }; + + buck7: BUCK7 { + regulator-name =3D "buck7"; + regulator-min-microvolt =3D <1605000>; + regulator-max-microvolt =3D <1995000>; + regulator-boot-on; + }; + + buck8: BUCK8 { + regulator-name =3D "buck8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1400000>; + regulator-boot-on; + }; + + ldo1: LDO1 { + regulator-name =3D "ldo1"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name =3D "ldo2"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name =3D "ldo3"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + }; + + ldo4: LDO4 { + regulator-name =3D "ldo4"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + }; + + ldo5: LDO5 { + regulator-name =3D "ldo5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + }; + + ldo6: LDO6 { + regulator-name =3D "ldo6"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + }; + + ldo7: LDO7 { + regulator-name =3D "ldo7"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + }; + }; + }; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width =3D <4>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + status =3D "okay"; +}; + +&usb3_phy0 { + status =3D "okay"; +}; + +&usb_dwc3_0 { + status =3D "okay"; + dr_mode =3D "otg"; +}; + +&usb3_phy1 { + status =3D "okay"; +}; + +&usb_dwc3_1 { + status =3D "okay"; + dr_mode =3D "host"; +}; + +&sai2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai2>; + assigned-clocks =3D <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI= 2>; + assigned-clock-parents =3D <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_P= LL1_OUT>; + assigned-clock-rates =3D <0>, <24576000>; + status =3D "okay"; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl-names =3D "default"; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins =3D < + MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins =3D < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins =3D < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins =3D < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins =3D < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins =3D < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins =3D < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins =3D < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; +}; --=20 2.17.1