From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 772D6C2D0C3 for ; Mon, 16 Dec 2019 17:47:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4980320717 for ; Mon, 16 Dec 2019 17:47:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="CZpv7hKh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726663AbfLPRr4 (ORCPT ); Mon, 16 Dec 2019 12:47:56 -0500 Received: from mail-pj1-f67.google.com ([209.85.216.67]:33574 "EHLO mail-pj1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726141AbfLPRrz (ORCPT ); Mon, 16 Dec 2019 12:47:55 -0500 Received: by mail-pj1-f67.google.com with SMTP id r67so3303881pjb.0 for ; Mon, 16 Dec 2019 09:47:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GsBjNENOsoqT3Ti/q8MjgvfcH88K3hdnCqSY0W84Ii0=; b=CZpv7hKhKwM6hd/Scc3APxW6cyON8Wk+eVweQIo7BJwpJlLycjtUkhILWu3EvtocUQ 1IVcQWu10k6j4vi718yHWUX8oDiS9CclHeARkvFOhA+uOdCPRcA6segAXc52LbA3c7CT FVJ8JG6bEMGcFSouHAQ+okgrtBSpbSXD8wk00= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GsBjNENOsoqT3Ti/q8MjgvfcH88K3hdnCqSY0W84Ii0=; b=DKqdNYIbFGq58eIFfqvbnGvKuUUk32JCIpHFIc4mM7/2aQyjsnkVIryN4ho98+Kxjr cMHiso7ThQFXl76RFnPam4E1uj2FpC5L7WrZAfpegFyvGwSQEsVvBDMGw5pNkPziatsV ek/b/55J83+7e8gmQWI30KkfuFbrBVoqyjB+jYZ7GuYOuHlrGb2YvbMxJYJZS+w9w3Iw csuVLX3gc1S19OMcErO3ZJ3FeXdWIOfgLmXEDqnXRVgfQSoanqnudabWy6K+7fRn0Vsh xAlDx6wPg1KyNYFndnrB2AL9rhaIQH4JSr+aj46Oy2gB93Adekw6ua8OZpbaBRmWeldy RLPQ== X-Gm-Message-State: APjAAAVs2R0wdrLskzMhJHZU4I7+sYGVvUvgsmrT533xLWflEIgNo/Lw MXKR1mQSnSoFd00GvRHA01Sctg== X-Google-Smtp-Source: APXvYqz+iv3tXMOmQkCoKsp3M01KIIk9WwfIebXGJsP426lmosp/FQUhk+gZEDSH93HQ5lak6qtuYQ== X-Received: by 2002:a17:902:b78b:: with SMTP id e11mr17804193pls.129.1576518475223; Mon, 16 Dec 2019 09:47:55 -0800 (PST) Received: from localhost.localdomain ([2405:201:c809:c7d5:6d28:a89:f9e1:1506]) by smtp.gmail.com with ESMTPSA id a6sm22342924pgg.25.2019.12.16.09.47.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Dec 2019 09:47:54 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Mark Rutland Cc: Manivannan Sadhasivam , Akash Gajjar , Tom Cubie , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 3/4] ARM: dts: rockchip: Add Radxa Dalang Carrier board Date: Mon, 16 Dec 2019 23:17:10 +0530 Message-Id: <20191216174711.17856-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191216174711.17856-1-jagan@amarulasolutions.com> References: <20191216174711.17856-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Carrier board often referred as baseboard. For making complete SBC or any other industrial boards, these carrier boards will used with associated SOMs. Radxa has Dalang carrier board which supports on board peripherals, ports like USB-2.0, USB-3.0, HDMI, MIPI DSI/CSI, eDP, Ethernet, WiFi, PCIe, USB-C, 40-Pin GPIO header and etc. Right now Dalang carrier board is using with two variants SBC, like Rock Pi N10 => VMARC RK3399Por SOM + Dalang carrier board Rock Pi N8 => VMARC RK3288 SOM + Dalang carrier board(+codec) So add this carrier board dtsi as a separate file in ARM directory, so-that the same can reuse it in both rk3288, rk3399pro variants of Rockchip SOMs. Signed-off-by: Jagan Teki --- Changes for v3: - none .../dts/rockchip-radxa-dalang-carrier.dtsi | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi new file mode 100644 index 000000000000..df3712aedf8a --- /dev/null +++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +#include + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&gmac { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio4>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + vqmmc-supply = <&vccio_sd>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = + <4 RK_PD6 0 &pcfg_pull_up>; + }; + }; +}; -- 2.18.0.321.gffc6fa0e3