From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37C48C43603 for ; Fri, 20 Dec 2019 10:17:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0ACDA24682 for ; Fri, 20 Dec 2019 10:17:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1576837072; bh=9y+vE6be/fQg89xEmZaoRg10l2d1ad2HMwJK38tcPPo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=VvEXvmDvdokud7bwW2y5EcJ1n1nwXQ8BiZt6Fc/ZbuJyEVibKgAXHxRhlbpX5m51b IlV1dpbXaSa8997k6pCoxTbKOIJPnfvHJESLKarY7UIcinTXq66dj88HVh7HbShnyd Vj0q2/YC8JODF1z70TyE19nizYa1tpp9D3+sBU08= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727435AbfLTKRv (ORCPT ); Fri, 20 Dec 2019 05:17:51 -0500 Received: from mail.kernel.org ([198.145.29.99]:53184 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727327AbfLTKRt (ORCPT ); Fri, 20 Dec 2019 05:17:49 -0500 Received: from localhost.localdomain (unknown [106.201.107.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id AC00F24685; Fri, 20 Dec 2019 10:17:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1576837068; bh=9y+vE6be/fQg89xEmZaoRg10l2d1ad2HMwJK38tcPPo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Pek5gpwXHKbqG0cPWLKoN1eHZXptlJROT1u799eqAhU4dZ5tI1/IKP2caoTQHk2b4 nEG/JO1B2/yVpEub4V/AnObpUSzvwqMjIQZDuERG9q+WxHIWCEqGwGislHMT43+NVx iKtMWxDgRTJwtqr8k70e6DXf3K8T/rRJi2qz4ZGc= From: Vinod Koul To: Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Can Guo , Jeffrey Hugo , linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] phy: qcom-qmp: Add optional SW reset Date: Fri, 20 Dec 2019 15:47:17 +0530 Message-Id: <20191220101719.3024693-4-vkoul@kernel.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191220101719.3024693-1-vkoul@kernel.org> References: <20191220101719.3024693-1-vkoul@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For V4 QMP UFS Phy, we need to assert reset bits, configure the phy and then deassert it, so add optional has_sw_reset flag and use that to configure the QPHY_SW_RESET register. Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 1196c85aa023..47a66d55107d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -168,6 +168,7 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = { static const unsigned int sm8150_ufsphy_regs_layout[] = { [QPHY_START_CTRL] = QPHY_V4_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_READY_STATUS, + [QPHY_SW_RESET] = QPHY_V4_SW_RESET, }; static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { @@ -1023,6 +1024,9 @@ struct qmp_phy_cfg { /* true, if PCS block has no separate SW_RESET register */ bool no_pcs_sw_reset; + + /* true if sw reset needs to be invoked */ + bool has_sw_reset; }; /** @@ -1391,6 +1395,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .is_dual_lane_phy = true, .no_pcs_sw_reset = true, + .has_sw_reset = true, }; static void qcom_qmp_phy_configure(void __iomem *base, @@ -1475,6 +1480,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); } + if (cfg->has_sw_reset) + qphy_setbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + if (cfg->has_phy_com_ctrl) qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], SW_PWRDN); @@ -1651,6 +1659,9 @@ static int qcom_qmp_phy_enable(struct phy *phy) if (cfg->has_phy_dp_com_ctrl) qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); + if (cfg->has_sw_reset) + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); -- 2.23.0