mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Ryan.Wanner@microchip.com, herbert@gondor.apana.org.au,
	davem@davemloft.net, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, nicolas.ferre@microchip.com,
	alexandre.belloni@bootlin.com, olivia@selenic.com
Cc: linux-crypto@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 8/9] ARM: dts: microchip: sama7d65: Add CAN bus support
Date: Sat, 7 Jun 2025 14:43:45 +0300	[thread overview]
Message-ID: <201c7188-eaf7-4492-84a6-66d839062d8d@tuxon.dev> (raw)
In-Reply-To: <445c4c72243f1ba85e3681ba026cfefaf6036890.1747077616.git.Ryan.Wanner@microchip.com>



On 12.05.2025 22:27, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
> 
> Add support for CAN bus to the SAMA7D65 SoC.
> 
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
>  arch/arm/boot/dts/microchip/sama7d65.dtsi | 80 +++++++++++++++++++++++
>  1 file changed, 80 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index 796909fa2368..a62d2ef9fcab 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> @@ -163,6 +163,86 @@ chipid@e0020000 {
>  			reg = <0xe0020000 0x8>;
>  		};
>  
> +		can0: can@e0828000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xe0828000 0x200>, <0x100000 0x7800>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 58>;
> +			assigned-clock-rates = <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		can1: can@e082c000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xe082c000 0x200>, <0x100000 0xbc00>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 59>;
> +			assigned-clock-rates = <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		can2: can@e0830000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xe0830000 0x200>, <0x100000 0x10000>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 60>;
> +			assigned-clock-rates = <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		can3: can@e0834000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xe0834000 0x200>, <0x110000 0x4400>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
> +			assigned-clock-rates = <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		can4: can@e0838000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xe0838000 0x200>, <0x110000 0x8800>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
> +			assigned-clock-rates = <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
>  		dma2: dma-controller@e1200000 {
>  			compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
>  			reg = <0xe1200000 0x1000>;


  reply	other threads:[~2025-06-07 11:43 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-12 19:27 [PATCH 0/9] SAMA7D65 Add support for Crypto, CAN and PWM Ryan.Wanner
2025-05-12 19:27 ` [PATCH 1/9] dt-bindings: crypto: add sama7d65 in Atmel AES Ryan.Wanner
2025-05-12 20:54   ` Rob Herring (Arm)
2025-06-07 11:40   ` Claudiu Beznea
2025-05-12 19:27 ` [PATCH 2/9] dt-bindings: crypto: add sama7d65 in Atmel SHA Ryan.Wanner
2025-05-12 20:54   ` Rob Herring (Arm)
2025-05-12 19:27 ` [PATCH 3/9] dt-bindings: crypto: add sama7d65 in Atmel TDES Ryan.Wanner
2025-05-12 20:54   ` Rob Herring (Arm)
2025-05-12 19:27 ` [PATCH 4/9] dt-bindings: rng: atmel,at91-trng: add sama7d65 TRNG Ryan.Wanner
2025-05-14 21:55   ` Rob Herring (Arm)
2025-06-07 11:41   ` Claudiu Beznea
2025-05-12 19:27 ` [PATCH 5/9] crypto: atmel - add support for AES and SHA IPs available on sama7d65 SoC Ryan.Wanner
2025-05-12 19:27 ` [PATCH 6/9] ARM: dts: microchip: sama7d65: Add crypto support Ryan.Wanner
2025-06-07 11:41   ` Claudiu Beznea
2025-05-12 19:27 ` [PATCH 7/9] ARM: dts: microchip: sama7d65: Add PWM support Ryan.Wanner
2025-06-07 11:42   ` Claudiu Beznea
2025-05-12 19:27 ` [PATCH 8/9] ARM: dts: microchip: sama7d65: Add CAN bus support Ryan.Wanner
2025-06-07 11:43   ` Claudiu Beznea [this message]
2025-05-12 19:27 ` [PATCH 9/9] ARM: dts: microchip: sama7d65: Enable CAN bus Ryan.Wanner
2025-06-07 11:44   ` Claudiu Beznea

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=201c7188-eaf7-4492-84a6-66d839062d8d@tuxon.dev \
    --to=claudiu.beznea@tuxon.dev \
    --cc=Ryan.Wanner@microchip.com \
    --cc=alexandre.belloni@bootlin.com \
    --cc=conor+dt@kernel.org \
    --cc=davem@davemloft.net \
    --cc=devicetree@vger.kernel.org \
    --cc=herbert@gondor.apana.org.au \
    --cc=krzk+dt@kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-crypto@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=nicolas.ferre@microchip.com \
    --cc=olivia@selenic.com \
    --cc=robh@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®