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Peter Anvin" , Janakarajan Natarajan , Jiri Olsa , Linus Torvalds , =?UTF-8?q?Martin=20Li=C5=A1ka?= , Namhyung Kim , Suravee Suthikulpanit , Thomas Gleixner , x86-ml , linux-kernel@vger.kernel.org, Babu Moger Subject: [PATCH internal v2] perf/x86/amd: Add missing L2 misses event spec to AMD Family 17h's event map Date: Wed, 8 Jan 2020 13:34:55 -0600 Message-Id: <20200108193455.29834-1-kim.phillips@amd.com> X-Mailer: git-send-email 2.24.1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SN4PR0501CA0035.namprd05.prod.outlook.com (2603:10b6:803:40::48) To SN6PR12MB2845.namprd12.prod.outlook.com (2603:10b6:805:75::33) MIME-Version: 1.0 Received: from fritz.amd.com (165.204.77.1) by SN4PR0501CA0035.namprd05.prod.outlook.com (2603:10b6:803:40::48) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2623.7 via Frontend Transport; Wed, 8 Jan 2020 19:35:03 +0000 X-Mailer: git-send-email 2.24.1 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 046e2fdf-964a-4f96-6ca6-08d79471dc59 X-MS-TrafficTypeDiagnostic: SN6PR12MB2656:|SN6PR12MB2656: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-Forefront-PRVS: 02760F0D1C X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(366004)(136003)(396003)(39860400002)(376002)(346002)(199004)(189003)(81156014)(81166006)(316002)(110136005)(6486002)(2906002)(36756003)(7416002)(8936002)(1076003)(966005)(4326008)(478600001)(8676002)(54906003)(6666004)(5660300002)(44832011)(52116002)(26005)(66556008)(66476007)(66946007)(956004)(86362001)(16526019)(2616005)(7696005)(186003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2656;H:SN6PR12MB2845.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RmH24K7cW07Vx7N7LmW0lWxLh/DshdA4svi0189+EG8F4fXitQPAwq+ftJ0s8yMkbJuUFJpG9Jkvt3pj+oiTfIBFIx6aiw0+0LfdyPJKW1zXfwhS7AkjFhb57mNgS7I+VOydx0GDVzUiFwYWWH5kdIbNpFd1zmBT0SFGeuEbLxKvERKItTiQoWfSMAavv9jXH5QXiOTS4gmZqL+eh2mm8sd+yPnUxQ9gfH5FPXkv+ApTRqEOccVXxgvPnSlcFr4ptmlnoq62SIKRP6IY25VOLCubVsUVQXGIN7TdqK0BRleKpVYRkWpPgFLCg34YC0++UVblae2pbFgbxkRQwKhTznJBjI0VRrRhSTT3W950scT+JGwoToQEnA9YfPs0+Bg11YGjVpybJY4K+gWPy6TrU5emKjV/AgolAyVadgdjP95EW37HETiA6iUDvWa7+sPxJO2QEV4+yKcdP8LUI5kquODzmkd08N4gXD1gr6xhwOw/FQsKyI5AVbxept6b8cl9aizoXbX/9QpSLfEs7LxV2w== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 046e2fdf-964a-4f96-6ca6-08d79471dc59 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2020 19:35:04.7006 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: o5f5w/aULyQNbOaZ3hF+jc4teeU83rJOnfwcJf53urtI1Zn8T5WUiWVVhdw6KdjZ/7tMCZBukLUxabFCh0lfnQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2656 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h"), claimed L2 misses were unsupported, due to them not being found in its referenced documentation, whose link has now moved [1]. That old documentation listed PMCx064 unit mask bit 3 as: "LsRdBlkC: LS Read Block C S L X Change to X Miss." and bit 0 as: "IcFillMiss: IC Fill Miss" We now have new public documentation [2] with improved descriptions, that clearly indicate what events those unit mask bits represent: Bit 3 now clearly states: "LsRdBlkC: Data Cache Req Miss in L2 (all types)" and bit 0 is: "IcFillMiss: Instruction Cache Req Miss in L2." So we can now add support for L2 misses in perf's genericised events as PMCx064 with both the above unit masks. [1] The commit's original documentation reference, "Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors", originally available here: https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf is now available here: https://developer.amd.com/wordpress/media/2017/11/54945_PPR_Family_17h_Models_00h-0Fh.pdf [2] "Processor Programming Reference (PPR) for Family 17h Model 31h, Revision B0 Processors", available here: https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf Cc: Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: H. Peter Anvin Cc: Ingo Molnar Cc: Janakarajan Natarajan Cc: Jiri Olsa Cc: Linus Torvalds Cc: Martin Liška Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suravee Suthikulpanit Cc: Thomas Gleixner Cc: x86-ml Cc: linux-kernel@vger.kernel.org Reported-by: Babu Moger Tested-by: Babu Moger Fixes: 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h") Signed-off-by: Kim Phillips --- arch/x86/events/amd/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index a7752cd78b89..dede714b46e8 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -246,6 +246,7 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60, + [PERF_COUNT_HW_CACHE_MISSES] = 0x0964, [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x0287, -- 2.24.1