From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F290C33CA2 for ; Wed, 8 Jan 2020 21:08:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 548F120705 for ; Wed, 8 Jan 2020 21:08:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b="bOdRKw3C" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727581AbgAHVIW (ORCPT ); Wed, 8 Jan 2020 16:08:22 -0500 Received: from o1.b.az.sendgrid.net ([208.117.55.133]:51247 "EHLO o1.b.az.sendgrid.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727263AbgAHVHu (ORCPT ); Wed, 8 Jan 2020 16:07:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=from:subject:in-reply-to:references:to:cc:content-type: content-transfer-encoding; s=001; bh=mPIGzETFyK+yy6AvuQViu61rlq4EFws+y7mGZ96sfzo=; b=bOdRKw3CE56+rxLYPC/ZQP0aQ2Rf8EhNnNtyg1xfcDeCqlfC+Y8ZdcNXo5BdOBR1BKlY WqDNfXAsQRJ2LdiktYj4AIeThjIOyciSqqZjjg4j8zoSg1AufhAMFG7Sok6+RYC6IQzLlw JrVsoVVbdovcpwOSrqoXGybXA1EsGCA7U= Received: by filterdrecv-p3mdw1-56c97568b5-d7vf5 with SMTP id filterdrecv-p3mdw1-56c97568b5-d7vf5-18-5E1644A6-6 2020-01-08 21:07:50.14129033 +0000 UTC m=+1974283.644180722 Received: from bionic.localdomain (unknown [98.128.173.80]) by ismtpd0005p1lon1.sendgrid.net (SG) with ESMTP id 5gIH8ZCXQJCZxUfJPXl_Sw Wed, 08 Jan 2020 21:07:49.944 +0000 (UTC) From: Jonas Karlman Subject: [PATCH v2 07/14] drm/rockchip: dw-hdmi: require valid vpll clock rate on rk3228/rk3328 Date: Wed, 08 Jan 2020 21:07:50 +0000 (UTC) Message-Id: <20200108210740.28769-8-jonas@kwiboo.se> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200108210740.28769-1-jonas@kwiboo.se> References: <20200108210740.28769-1-jonas@kwiboo.se> X-SG-EID: =?us-ascii?Q?TdbjyGynYnRZWhH+7lKUQJL+ZxmxpowvO2O9SQF5CwCVrYgcwUXgU5DKUU3QxA?= =?us-ascii?Q?fZekEeQsTe+RrMu3cja6a0h9fq3wHH7v6C53qgA?= =?us-ascii?Q?YlW1v7dKuNjfj9RgmNCofuXzEMYVHRoz6lVvBjE?= =?us-ascii?Q?A4xTi17C8zi=2Fp2rtoJpot8cXaQLOJJaAO7vPEqA?= =?us-ascii?Q?ZODRulaZFl1P7H1CNJOvZQ97hAc47ldfcovtAqE?= =?us-ascii?Q?OeiSorFXVV8fuU9PXx8AqxoJ14Xm5Xxw1Wuze88?= =?us-ascii?Q?XDmdHRdrYkzhnu7r8dyiQ=3D=3D?= To: Heiko Stuebner , Sandy Huang Cc: Jonas Karlman , Kishon Vijay Abraham I , Zheng Yang , linux-rockchip@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org RK3228/RK3328 can only support clock rates defined in the pre pll table. Lets validate the mode clock rate against the pre pll config and filter out any mode with a clock rate returning error from clk_round_rate(). Signed-off-by: Jonas Karlman --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index fae38b323a0c..45fcdce3f27f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -245,6 +245,22 @@ static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) { } +static enum drm_mode_status +dw_hdmi_rockchip_encoder_mode_valid(struct drm_encoder *encoder, + const struct drm_display_mode *mode) +{ + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + long rate; + + if (hdmi->vpll_clk) { + rate = clk_round_rate(hdmi->vpll_clk, mode->clock * 1000); + if (rate < 0) + return MODE_CLOCK_RANGE; + } + + return MODE_OK; +} + static bool dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, @@ -306,6 +322,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, } static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { + .mode_valid = dw_hdmi_rockchip_encoder_mode_valid, .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, .mode_set = dw_hdmi_rockchip_encoder_mode_set, .enable = dw_hdmi_rockchip_encoder_enable, -- 2.17.1