From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B69ABC282DD for ; Fri, 10 Jan 2020 14:22:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 89A8D2077C for ; Fri, 10 Jan 2020 14:22:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="Gp+lCFbh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728152AbgAJOW6 (ORCPT ); Fri, 10 Jan 2020 09:22:58 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:59604 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727803AbgAJOW6 (ORCPT ); Fri, 10 Jan 2020 09:22:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=/LqUWTGBt5gIEmNEJ7QzFyPyiWRNbMxwiltxq0x8igc=; b=Gp+lCFbhq8KoEC210hcrrMI+wF 0JmIiELjl9bsPWXOe+seRjm5/SPB27amgsTcYWk3K7slz6nTL7Ap4HOtQKZQxxSen6qMer/4I6JEo yAvQ+UulpPXYSX6w61WiKyIYOL/UICkN8rDzumQnp6aSzIjQp9ojDzMowUF4uRGZOLNk=; Received: from andrew by vps0.lunn.ch with local (Exim 4.93) (envelope-from ) id 1ipvBa-0007bd-5w; Fri, 10 Jan 2020 15:22:50 +0100 Date: Fri, 10 Jan 2020 15:22:50 +0100 From: Andrew Lunn To: Andre Przywara Cc: "David S . Miller" , Radhey Shyam Pandey , Michal Simek , Robert Hancock , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 12/14] net: axienet: Autodetect 64-bit DMA capability Message-ID: <20200110142250.GH19739@lunn.ch> References: <20200110115415.75683-1-andre.przywara@arm.com> <20200110115415.75683-13-andre.przywara@arm.com> <20200110140852.GF19739@lunn.ch> <20200110141303.2e5863ab@donnerap.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200110141303.2e5863ab@donnerap.cambridge.arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 10, 2020 at 02:13:03PM +0000, Andre Przywara wrote: > On Fri, 10 Jan 2020 15:08:52 +0100 > Andrew Lunn wrote: > > Hi Andrew, > > thanks for having a look! > > > > To autodetect this configuration, at probe time we write all 1's to such > > > an MSB register, and see if any bits stick. > > > > So there is no register you can read containing the IP version? > > There is, and I actually read this before doing this check. But the 64-bit DMA capability is optional even in this revision. It depends on what you give it as the address width. If you say 32, the IP config tool disables the 64-bit capability completely, so it stays compatible with older revisions. > Anything beyond 32 will enable the MSB register and will also require you to write to them. So you are saying there is no way to enumerate the synthesised configuration of the IP. Great :-( Do Xilinx at least document you can discover the DMA size by writing into these upper bits? Does Xilinx own 'vendor crap' driver do this? Thanks Andrew