From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.0 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31ABEC33CB2 for ; Tue, 14 Jan 2020 17:23:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 05AB82465A for ; Tue, 14 Jan 2020 17:23:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="FrxsU/ic" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728650AbgANRX3 (ORCPT ); Tue, 14 Jan 2020 12:23:29 -0500 Received: from mail25.static.mailgun.info ([104.130.122.25]:36907 "EHLO mail25.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726053AbgANRX3 (ORCPT ); Tue, 14 Jan 2020 12:23:29 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1579022608; h=In-Reply-To: Content-Type: MIME-Version: References: Message-ID: Subject: Cc: To: From: Date: Sender; bh=ExKH6Qx5NOKiFzMpvDrIYdTOxCKfXj+v5nlEnciqC7E=; b=FrxsU/iclqknQz+4bsUWuYH77IJxWCX3+P6BZ/TjKsCfpqbwmOb8nfAzotI29UnB8WwbCd1l noC/utySbWwoSa9GNcNLEYKk7HEk4p4PwGqpCbxI23ufJ0Ztfk++wjM9Y2rJTngp/Aris7QZ KAHEnzlw6VVCCgOTAPrNoPjzjSQ= X-Mailgun-Sending-Ip: 104.130.122.25 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e1df90c.7fad57f612d0-smtp-out-n02; Tue, 14 Jan 2020 17:23:24 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 1716EC447A1; Tue, 14 Jan 2020 17:23:23 +0000 (UTC) Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 87268C433CB; Tue, 14 Jan 2020 17:23:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 87268C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Tue, 14 Jan 2020 10:23:19 -0700 From: Jordan Crouse To: Rob Clark Cc: Brian Ho , freedreno , David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Rob Clark , Daniel Vetter , Kristian Kristensen , Sean Paul Subject: Re: [Freedreno] [PATCH 2/2] drm/msm: Add MSM_WAIT_IOVA ioctl Message-ID: <20200114172319.GA2371@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Rob Clark , Brian Ho , freedreno , David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Rob Clark , Daniel Vetter , Kristian Kristensen , Sean Paul References: <20200113153605.52350-1-brian@brkho.com> <20200113153605.52350-3-brian@brkho.com> <20200113175148.GC26711@jcrouse1-lnx.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 14, 2020 at 08:52:43AM -0800, Rob Clark wrote: > On Mon, Jan 13, 2020 at 9:51 AM Jordan Crouse wrote: > > > > On Mon, Jan 13, 2020 at 10:36:05AM -0500, Brian Ho wrote: > > > + > > > + vaddr = base_vaddr + args->offset; > > > + > > > + /* Assumes WC mapping */ > > > + ret = wait_event_interruptible_timeout( > > > + gpu->event, *vaddr >= args->value, remaining_jiffies); > > > > I feel like a barrier might be needed before checking *vaddr just in case you > > get the interrupt and wake up the queue before the write posts from the > > hardware. > > > > if the gpu is doing posted (or cached) writes, I don't think there is > even a CPU side barrier primitive that could wait for that? I think > we rely on the GPU not interrupting the CPU until the write is posted Once the GPU puts the write on the bus then it is up to the whims of the CPU architecture. If the writes are being done out of order you run a chance of firing the interrupt and making it all the way to your handler before the writes catch up. Since you are scheduling and doing a bunch of things in between you probably don't need to worry but if you start missing events and you don't know why then this could be why. A rmb() would give you piece of mind at the cost of being Yet Another Barrier (TM). Jordan > BR, > -R > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project